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56 lines
1.6 KiB
Diff
56 lines
1.6 KiB
Diff
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From 1dc069ffadf4ce7817a716f9df2f480254e9b01d Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Jo=C3=A3o=20M=C3=A1rio=20Domingos?=
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<joao.mario@tecnico.ulisboa.pt>
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Date: Tue, 16 Nov 2021 15:48:10 +0000
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Subject: [PATCH 074/116] RISC-V: Support CPUID for risc-v in perf
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This patch creates the header.c file for the risc-v architecture and introduces support for
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PMU identification through sysfs.
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It is now possible to configure pmu-events in risc-v.
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Depends on patch [1], that introduces the id sysfs file.
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Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
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Signed-off-by: minda.chen <minda.chen@starfivetech.com>
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---
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drivers/perf/riscv_pmu.c | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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--- a/drivers/perf/riscv_pmu.c
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+++ b/drivers/perf/riscv_pmu.c
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@@ -18,6 +18,23 @@
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#include <asm/sbi.h>
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+PMU_FORMAT_ATTR(event, "config:0-63");
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+
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+static struct attribute *riscv_arch_formats_attr[] = {
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+ &format_attr_event.attr,
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+ NULL,
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+};
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+
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+static struct attribute_group riscv_pmu_format_group = {
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+ .name = "format",
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+ .attrs = riscv_arch_formats_attr,
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+};
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+
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+static const struct attribute_group *riscv_pmu_attr_groups[] = {
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+ &riscv_pmu_format_group,
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+ NULL,
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+};
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+
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static bool riscv_perf_user_access(struct perf_event *event)
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{
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return ((event->attr.type == PERF_TYPE_HARDWARE) ||
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@@ -410,6 +427,7 @@ struct riscv_pmu *riscv_pmu_alloc(void)
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cpuc->events[i] = NULL;
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}
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pmu->pmu = (struct pmu) {
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+ .attr_groups = riscv_pmu_attr_groups,
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.event_init = riscv_pmu_event_init,
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.event_mapped = riscv_pmu_event_mapped,
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.event_unmapped = riscv_pmu_event_unmapped,
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