mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-26 17:01:14 +00:00
26 lines
946 B
Diff
26 lines
946 B
Diff
|
From 3224569a3e279bbeae4e975dfa1a890f3f595239 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
|
||
|
|
Date: Fri, 10 May 2024 15:18:44 +0100
|
||
|
|
Subject: [PATCH 1176/1215] dt-bindings: clk: rp1: Add clocks representing MIPI
|
||
|
|
DSI byteclock
|
||
|
|
|
||
|
|
Define two new RP1 clocks, representing the MIPI DSI byteclock
|
||
|
|
sources for the dividers used to generate MIPI[01] DPI pixel clocks.
|
||
|
|
(Previously they were represented by "fake" fixed clocks sources).
|
||
|
|
|
||
|
|
Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
|
||
|
|
---
|
||
|
|
include/dt-bindings/clock/rp1.h | 4 ++++
|
||
|
|
1 file changed, 4 insertions(+)
|
||
|
|
|
||
|
|
--- a/include/dt-bindings/clock/rp1.h
|
||
|
|
+++ b/include/dt-bindings/clock/rp1.h
|
||
|
|
@@ -54,3 +54,7 @@
|
||
|
|
/* Extra PLL output channels - RP1B0 only */
|
||
|
|
#define RP1_PLL_VIDEO_PRI_PH 43
|
||
|
|
#define RP1_PLL_AUDIO_TERN 44
|
||
|
|
+
|
||
|
|
+/* MIPI clocks managed by the DSI driver */
|
||
|
|
+#define RP1_CLK_MIPI0_DSI_BYTECLOCK 45
|
||
|
|
+#define RP1_CLK_MIPI1_DSI_BYTECLOCK 46
|