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62 lines
2.0 KiB
Diff
62 lines
2.0 KiB
Diff
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From 3cbd661b811bda9a33253f65b5cf0c25b8c5447f Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Date: Thu, 30 Nov 2023 16:19:29 +0100
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Subject: [PATCH 1020/1024] riscv: dts: starfive: Add pool for coherent DMA
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memory on JH7100 boards
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The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers
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expect to be able to allocate coherent memory for DMA descriptors and
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such. However on the JH7100 DDR memory appears twice in the physical
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memory map, once cached and once uncached:
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0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached
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0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached
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To use this uncached region we create a global DMA memory pool there and
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reserve the corresponding area in the cached region.
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However the uncached region is fully above the 32bit address limit, so add
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a dma-ranges map so the DMA address used for peripherals is still in the
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regular cached region below the limit.
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Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
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Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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.../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
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1 file changed, 24 insertions(+)
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--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
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@@ -39,6 +39,30 @@
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label = "ack";
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};
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};
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+
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+ reserved-memory {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ dma-reserved@fa000000 {
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+ reg = <0x0 0xfa000000 0x0 0x1000000>;
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+ no-map;
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+ };
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+
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+ linux,dma@107a000000 {
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+ compatible = "shared-dma-pool";
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+ reg = <0x10 0x7a000000 0x0 0x1000000>;
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+ no-map;
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+ linux,dma-default;
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+ };
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+ };
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+
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+ soc {
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+ dma-ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x7a000000>,
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+ <0x00 0xfa000000 0x10 0x7a000000 0x00 0x01000000>,
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+ <0x00 0xfb000000 0x00 0xfb000000 0x07 0x85000000>;
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+ };
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};
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&gpio {
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