2018-11-02 03:21:57 +00:00
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From c503e92983f2e18c1e18e21b15d5bedd6d0be8ac Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Tue, 30 Oct 2018 18:26:56 +0800
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Subject: [PATCH 33/40] pcie: support layerscape
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This is an integrated patch of pcie for layerscape
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Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Signed-off-by: Po Liu <po.liu@nxp.com>
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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---
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.../bindings/pci/layerscape-pci.txt | 14 +-
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arch/arm/kernel/bios32.c | 43 ++++++
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arch/arm64/kernel/pci.c | 43 ++++++
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drivers/misc/pci_endpoint_test.c | 20 +--
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drivers/pci/dwc/Kconfig | 8 ++
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drivers/pci/dwc/pci-layerscape.c | 132 +++++++++++++++++-
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drivers/pci/endpoint/functions/pci-epf-test.c | 2 +-
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drivers/pci/endpoint/pci-epf-core.c | 8 +-
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drivers/pci/pcie/portdrv_core.c | 29 ++++
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drivers/pci/quirks.c | 15 ++
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include/linux/pci.h | 1 +
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11 files changed, 292 insertions(+), 23 deletions(-)
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--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
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+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
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@@ -18,11 +18,16 @@ Required properties:
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"fsl,ls2088a-pcie"
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"fsl,ls1088a-pcie"
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"fsl,ls1046a-pcie"
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+ "fsl,ls1012a-pcie"
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- reg: base addresses and lengths of the PCIe controller register blocks.
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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-- interrupt-names: Must include the following entries:
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- "intr": The interrupt that is asserted for controller interrupts
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+- interrupt-names: It could include the following entries:
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+ "aer": Asserted for aer interrupt when chip support the aer interrupt with
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+ none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
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+ "pme": Asserted for pme interrupt when chip support the pme interrupt with
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+ none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
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+ ......
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- fsl,pcie-scfg: Must include two entries.
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The first entry must be a link to the SCFG device node
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The second entry must be '0' or '1' based on physical PCIe controller index.
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@@ -38,8 +43,9 @@ Example:
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reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
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0x40 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
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- interrupt-names = "intr";
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+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
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+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
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+ interrupt-names = "aer", "pme";
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fsl,pcie-scfg = <&scfg 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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--- a/arch/arm/kernel/bios32.c
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+++ b/arch/arm/kernel/bios32.c
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@@ -12,6 +12,8 @@
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/io.h>
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+#include <linux/of_irq.h>
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+#include <linux/pcieport_if.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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@@ -65,6 +67,47 @@ void pcibios_report_status(u_int status_
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}
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/*
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+ * Check device tree if the service interrupts are there
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+ */
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+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
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+{
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+ int ret, count = 0;
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+ struct device_node *np = NULL;
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+
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+ if (dev->bus->dev.of_node)
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+ np = dev->bus->dev.of_node;
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+
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+ if (np == NULL)
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+ return 0;
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+
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+ if (!IS_ENABLED(CONFIG_OF_IRQ))
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+ return 0;
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+
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+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
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+ * request irq for aer
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+ */
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+ if (mask & PCIE_PORT_SERVICE_AER) {
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+ ret = of_irq_get_byname(np, "aer");
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+ if (ret > 0) {
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+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
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+ count++;
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+ }
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+ }
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+
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+ if (mask & PCIE_PORT_SERVICE_PME) {
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+ ret = of_irq_get_byname(np, "pme");
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+ if (ret > 0) {
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+ irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
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+ count++;
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+ }
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+ }
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+
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+ /* TODO: add more service interrupts if there it is in the device tree*/
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+
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+ return count;
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+}
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+
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+/*
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* We don't use this to fix the device, but initialisation of it.
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* It's not the correct use for this, but it works.
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* Note that the arbiter/ISA bridge appears to be buggy, specifically in
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--- a/arch/arm64/kernel/pci.c
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+++ b/arch/arm64/kernel/pci.c
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@@ -17,6 +17,8 @@
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#include <linux/mm.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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+#include <linux/of_irq.h>
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+#include <linux/pcieport_if.h>
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#include <linux/pci.h>
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#include <linux/pci-acpi.h>
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#include <linux/pci-ecam.h>
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@@ -36,6 +38,47 @@ int pcibios_alloc_irq(struct pci_dev *de
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#endif
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/*
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+ * Check device tree if the service interrupts are there
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+ */
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+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
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+{
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+ int ret, count = 0;
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+ struct device_node *np = NULL;
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+
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+ if (dev->bus->dev.of_node)
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+ np = dev->bus->dev.of_node;
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+
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+ if (np == NULL)
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+ return 0;
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+
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+ if (!IS_ENABLED(CONFIG_OF_IRQ))
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+ return 0;
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+
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+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
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+ * request irq for aer
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+ */
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+ if (mask & PCIE_PORT_SERVICE_AER) {
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+ ret = of_irq_get_byname(np, "aer");
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+ if (ret > 0) {
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+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
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+ count++;
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+ }
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+ }
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+
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+ if (mask & PCIE_PORT_SERVICE_PME) {
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+ ret = of_irq_get_byname(np, "pme");
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+ if (ret > 0) {
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+ irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
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+ count++;
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+ }
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+ }
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+
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+ /* TODO: add more service interrupts if there it is in the device tree*/
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+
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+ return count;
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+}
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+
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+/*
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* raw_pci_read/write - Platform-specific PCI config space access.
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*/
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int raw_pci_read(unsigned int domain, unsigned int bus,
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--- a/drivers/misc/pci_endpoint_test.c
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+++ b/drivers/misc/pci_endpoint_test.c
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@@ -97,6 +97,8 @@ struct pci_endpoint_test {
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struct miscdevice miscdev;
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enum pci_barno test_reg_bar;
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size_t alignment;
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+ char name[20];
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+ int irq_num;
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};
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struct pci_endpoint_test_data {
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@@ -454,9 +456,7 @@ static int pci_endpoint_test_probe(struc
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{
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int i;
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int err;
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- int irq = 0;
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int id;
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- char name[20];
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enum pci_barno bar;
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void __iomem *base;
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struct device *dev = &pdev->dev;
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@@ -501,19 +501,19 @@ static int pci_endpoint_test_probe(struc
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pci_set_master(pdev);
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if (!no_msi) {
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- irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
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- if (irq < 0)
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+ test->irq_num = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
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+ if (test->irq_num < 0)
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dev_err(dev, "failed to get MSI interrupts\n");
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}
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- err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
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+ err = request_irq(pdev->irq, pci_endpoint_test_irqhandler,
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IRQF_SHARED, DRV_MODULE_NAME, test);
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if (err) {
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dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
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goto err_disable_msi;
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}
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- for (i = 1; i < irq; i++) {
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+ for (i = 1; i < test->irq_num; i++) {
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err = devm_request_irq(dev, pdev->irq + i,
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pci_endpoint_test_irqhandler,
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IRQF_SHARED, DRV_MODULE_NAME, test);
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@@ -548,10 +548,10 @@ static int pci_endpoint_test_probe(struc
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goto err_iounmap;
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}
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- snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
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+ snprintf(test->name, sizeof(test->name), DRV_MODULE_NAME ".%d", id);
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misc_device = &test->miscdev;
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misc_device->minor = MISC_DYNAMIC_MINOR;
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- misc_device->name = name;
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+ misc_device->name = test->name;
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misc_device->fops = &pci_endpoint_test_fops,
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err = misc_register(misc_device);
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@@ -584,6 +584,7 @@ err_disable_pdev:
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static void pci_endpoint_test_remove(struct pci_dev *pdev)
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{
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int id;
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+ int i;
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enum pci_barno bar;
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struct pci_endpoint_test *test = pci_get_drvdata(pdev);
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struct miscdevice *misc_device = &test->miscdev;
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@@ -599,6 +600,8 @@ static void pci_endpoint_test_remove(str
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if (test->bar[bar])
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pci_iounmap(pdev, test->bar[bar]);
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}
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+ for (i = 0; i < test->irq_num; i++)
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+ free_irq(pdev->irq + i, test);
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pci_disable_msi(pdev);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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@@ -607,6 +610,7 @@ static void pci_endpoint_test_remove(str
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static const struct pci_device_id pci_endpoint_test_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
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--- a/drivers/pci/dwc/Kconfig
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+++ b/drivers/pci/dwc/Kconfig
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@@ -111,6 +111,14 @@ config PCI_LAYERSCAPE
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help
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Say Y here if you want PCIe controller support on Layerscape SoCs.
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+config PCI_LAYERSCAPE_EP
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+ bool "PCI layerscape Endpoint Mode"
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+ depends on PCI_ENDPOINT
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+ select PCIE_DW_EP
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+ help
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+ Enables support for the PCIe controller in the layerscape SoC to work in
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+ endpoint mode.
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+
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config PCI_HISI
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depends on OF && ARM64
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bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
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--- a/drivers/pci/dwc/pci-layerscape.c
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+++ b/drivers/pci/dwc/pci-layerscape.c
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@@ -33,8 +33,15 @@
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/* PEX Internal Configuration Registers */
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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+#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
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+#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
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+#define PCIE_DBI2_BASE 0x1000 /* DBI2 base address*/
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+#define PCIE_MSI_MSG_DATA_OFF 0x5c /* MSI Data register address*/
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+#define PCIE_MSI_OB_SIZE 4096
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+#define PCIE_MSI_ADDR_OFFSET (1024 * 1024)
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#define PCIE_IATU_NUM 6
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+#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
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struct ls_pcie_drvdata {
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u32 lut_offset;
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@@ -44,12 +51,20 @@ struct ls_pcie_drvdata {
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const struct dw_pcie_ops *dw_pcie_ops;
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};
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+struct ls_pcie_ep {
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+ dma_addr_t msi_phys_addr;
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+ void __iomem *msi_virt_addr;
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+ u64 msi_msg_addr;
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+ u16 msi_msg_data;
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+};
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+
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struct ls_pcie {
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struct dw_pcie *pci;
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void __iomem *lut;
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struct regmap *scfg;
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const struct ls_pcie_drvdata *drvdata;
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int index;
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+ struct ls_pcie_ep *pcie_ep;
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};
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#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
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@@ -124,6 +139,14 @@ static int ls_pcie_link_up(struct dw_pci
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return 1;
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}
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+/* Forward error response of outbound non-posted requests */
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+static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
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+{
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+ struct dw_pcie *pci = pcie->pci;
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+
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+ iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
static int ls_pcie_host_init(struct pcie_port *pp)
|
|
|
|
{
|
|
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
|
|
|
@@ -135,6 +158,7 @@ static int ls_pcie_host_init(struct pcie
|
|
|
|
* dw_pcie_setup_rc() will reconfigure the outbound windows.
|
|
|
|
*/
|
|
|
|
ls_pcie_disable_outbound_atus(pcie);
|
|
|
|
+ ls_pcie_fix_error_response(pcie);
|
|
|
|
|
|
|
|
dw_pcie_dbi_ro_wr_en(pci);
|
|
|
|
ls_pcie_clear_multifunction(pcie);
|
|
|
|
@@ -253,6 +277,7 @@ static struct ls_pcie_drvdata ls2088_drv
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id ls_pcie_of_match[] = {
|
|
|
|
+ { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
|
|
|
|
{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
|
|
|
|
{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
|
|
|
|
{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
|
|
|
|
@@ -263,6 +288,99 @@ static const struct of_device_id ls_pcie
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|
|
{ },
|
|
|
|
};
|
|
|
|
|
|
|
|
+static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep)
|
|
|
|
+{
|
|
|
|
+ iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
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|
|
|
+ enum pci_epc_irq_type type, u8 interrupt_num)
|
|
|
|
+{
|
|
|
|
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
|
|
|
+ struct ls_pcie *pcie = to_ls_pcie(pci);
|
|
|
|
+ struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
|
|
|
|
+ u32 free_win;
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|
|
|
+
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|
|
|
+ /* get the msi message address and msi message data */
|
|
|
|
+ pcie_ep->msi_msg_addr = ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_L32) |
|
|
|
|
+ (((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) << 32);
|
|
|
|
+ pcie_ep->msi_msg_data = ioread16(pci->dbi_base + PCIE_MSI_MSG_DATA_OFF);
|
|
|
|
+
|
|
|
|
+ /* request and config the outband window for msi */
|
|
|
|
+ free_win = find_first_zero_bit(&ep->ob_window_map,
|
|
|
|
+ sizeof(ep->ob_window_map));
|
|
|
|
+ if (free_win >= ep->num_ob_windows) {
|
|
|
|
+ dev_err(pci->dev, "no free outbound window\n");
|
|
|
|
+ return -ENOMEM;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
|
|
|
|
+ pcie_ep->msi_phys_addr,
|
|
|
|
+ pcie_ep->msi_msg_addr,
|
|
|
|
+ PCIE_MSI_OB_SIZE);
|
|
|
|
+
|
|
|
|
+ set_bit(free_win, &ep->ob_window_map);
|
|
|
|
+
|
|
|
|
+ /* generate the msi interrupt */
|
|
|
|
+ ls_pcie_raise_msi_irq(pcie_ep);
|
|
|
|
+
|
|
|
|
+ /* release the outband window of msi */
|
|
|
|
+ dw_pcie_disable_atu(pci, free_win, DW_PCIE_REGION_OUTBOUND);
|
|
|
|
+ clear_bit(free_win, &ep->ob_window_map);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static struct dw_pcie_ep_ops pcie_ep_ops = {
|
|
|
|
+ .raise_irq = ls_pcie_raise_irq,
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
|
|
|
|
+ struct platform_device *pdev)
|
|
|
|
+{
|
|
|
|
+ struct dw_pcie *pci = pcie->pci;
|
|
|
|
+ struct device *dev = pci->dev;
|
|
|
|
+ struct dw_pcie_ep *ep;
|
|
|
|
+ struct ls_pcie_ep *pcie_ep;
|
|
|
|
+ struct resource *cfg_res;
|
|
|
|
+ int ret;
|
|
|
|
+
|
|
|
|
+ ep = &pci->ep;
|
|
|
|
+ ep->ops = &pcie_ep_ops;
|
|
|
|
+
|
|
|
|
+ pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
|
|
|
|
+ if (!pcie_ep)
|
|
|
|
+ return -ENOMEM;
|
|
|
|
+
|
|
|
|
+ pcie->pcie_ep = pcie_ep;
|
|
|
|
+
|
|
|
|
+ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
|
|
|
|
+ if (cfg_res) {
|
|
|
|
+ ep->phys_base = cfg_res->start;
|
|
|
|
+ ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE;
|
|
|
|
+ } else {
|
|
|
|
+ dev_err(dev, "missing *config* space\n");
|
|
|
|
+ return -ENODEV;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET;
|
|
|
|
+
|
|
|
|
+ pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr,
|
|
|
|
+ PCIE_MSI_OB_SIZE);
|
|
|
|
+ if (!pcie_ep->msi_virt_addr) {
|
|
|
|
+ dev_err(dev, "failed to map MSI outbound region\n");
|
|
|
|
+ return -ENOMEM;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ ret = dw_pcie_ep_init(ep);
|
|
|
|
+ if (ret) {
|
|
|
|
+ dev_err(dev, "failed to initialize endpoint\n");
|
|
|
|
+ return ret;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
static int __init ls_add_pcie_port(struct ls_pcie *pcie)
|
|
|
|
{
|
|
|
|
struct dw_pcie *pci = pcie->pci;
|
|
|
|
@@ -309,18 +427,18 @@ static int __init ls_pcie_probe(struct p
|
|
|
|
if (IS_ERR(pci->dbi_base))
|
|
|
|
return PTR_ERR(pci->dbi_base);
|
|
|
|
|
|
|
|
- pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
|
|
|
|
+ pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
|
|
|
|
|
|
|
|
- if (!ls_pcie_is_bridge(pcie))
|
|
|
|
- return -ENODEV;
|
|
|
|
+ pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, pcie);
|
|
|
|
|
|
|
|
- ret = ls_add_pcie_port(pcie);
|
|
|
|
- if (ret < 0)
|
|
|
|
- return ret;
|
|
|
|
+ if (!ls_pcie_is_bridge(pcie))
|
|
|
|
+ ret = ls_add_pcie_ep(pcie, pdev);
|
|
|
|
+ else
|
|
|
|
+ ret = ls_add_pcie_port(pcie);
|
|
|
|
|
|
|
|
- return 0;
|
|
|
|
+ return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver ls_pcie_driver = {
|
|
|
|
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
|
|
|
|
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
|
|
|
|
@@ -471,7 +471,7 @@ static int pci_epf_test_probe(struct pci
|
|
|
|
const struct pci_epf_device_id *match;
|
|
|
|
struct pci_epf_test_data *data;
|
|
|
|
enum pci_barno test_reg_bar = BAR_0;
|
|
|
|
- bool linkup_notifier = true;
|
|
|
|
+ bool linkup_notifier = false;
|
|
|
|
|
|
|
|
match = pci_epf_match_device(pci_epf_test_ids, epf);
|
|
|
|
data = (struct pci_epf_test_data *)match->driver_data;
|
|
|
|
--- a/drivers/pci/endpoint/pci-epf-core.c
|
|
|
|
+++ b/drivers/pci/endpoint/pci-epf-core.c
|
|
|
|
@@ -104,8 +104,8 @@ void pci_epf_free_space(struct pci_epf *
|
|
|
|
if (!addr)
|
|
|
|
return;
|
|
|
|
|
|
|
|
- dma_free_coherent(dev, epf->bar[bar].size, addr,
|
|
|
|
- epf->bar[bar].phys_addr);
|
|
|
|
+ free_pages((unsigned long)addr,
|
|
|
|
+ get_order(epf->bar[bar].size));
|
|
|
|
|
|
|
|
epf->bar[bar].phys_addr = 0;
|
|
|
|
epf->bar[bar].size = 0;
|
|
|
|
@@ -129,7 +129,9 @@ void *pci_epf_alloc_space(struct pci_epf
|
|
|
|
size = 128;
|
|
|
|
size = roundup_pow_of_two(size);
|
|
|
|
|
|
|
|
- space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
|
|
|
|
+ space = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
|
|
|
+ get_order(size));
|
|
|
|
+ phys_addr = virt_to_phys(space);
|
|
|
|
if (!space) {
|
|
|
|
dev_err(dev, "failed to allocate mem space\n");
|
|
|
|
return NULL;
|
|
|
|
--- a/drivers/pci/pcie/portdrv_core.c
|
|
|
|
+++ b/drivers/pci/pcie/portdrv_core.c
|
|
|
|
@@ -45,6 +45,20 @@ static void release_pcie_device(struct d
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
+ * pcibios_check_service_irqs - check irqs in the device tree
|
|
|
|
+ * @dev: PCI Express port to handle
|
|
|
|
+ * @irqs: Array of irqs to populate
|
|
|
|
+ * @mask: Bitmask of port capabilities returned by get_port_device_capability()
|
|
|
|
+ *
|
|
|
|
+ * Return value: 0 means no service irqs in the device tree
|
|
|
|
+ *
|
|
|
|
+ */
|
|
|
|
+int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
|
|
|
|
+{
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+/**
|
|
|
|
* pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode
|
|
|
|
* for given port
|
|
|
|
* @dev: PCI Express port to handle
|
|
|
|
@@ -185,10 +199,25 @@ out_free_irqs:
|
|
|
|
static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
|
|
|
|
{
|
|
|
|
int ret, i;
|
|
|
|
+ int irq = -1;
|
|
|
|
|
|
|
|
for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
|
|
|
|
irqs[i] = -1;
|
|
|
|
|
|
|
|
+ /* Check if some platforms owns independent irq pins for AER/PME etc.
|
|
|
|
+ * Some platforms may own independent AER/PME interrupts and set
|
|
|
|
+ * them in the device tree file.
|
|
|
|
+ */
|
|
|
|
+ ret = pcibios_check_service_irqs(dev, irqs, mask);
|
|
|
|
+ if (ret) {
|
|
|
|
+ if (dev->irq)
|
|
|
|
+ irq = dev->irq;
|
|
|
|
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
|
|
|
|
+ if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
|
|
|
|
+ irqs[i] = irq;
|
|
|
|
+ return 0;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
/*
|
|
|
|
* If we support PME or hotplug, but we can't use MSI/MSI-X for
|
|
|
|
* them, we have to fall back to INTx or other interrupts, e.g., a
|
|
|
|
--- a/drivers/pci/quirks.c
|
|
|
|
+++ b/drivers/pci/quirks.c
|
|
|
|
@@ -3376,6 +3376,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
|
|
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
|
|
|
|
|
|
|
|
+/*
|
|
|
|
+ * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
|
|
|
|
+ * bus reset. Link state of device does not comes UP and so config space
|
|
|
|
+ * never accessible again.
|
|
|
|
+ */
|
|
|
|
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
|
|
|
|
+
|
|
|
|
static void quirk_no_pm_reset(struct pci_dev *dev)
|
|
|
|
{
|
|
|
|
/*
|
2019-04-18 13:04:42 +00:00
|
|
|
@@ -4859,3 +4866,11 @@ static void quirk_no_ats(struct pci_dev
|
2018-11-02 03:21:57 +00:00
|
|
|
/* AMD Stoney platform GPU */
|
|
|
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
|
|
|
|
#endif /* CONFIG_PCI_ATS */
|
|
|
|
+
|
|
|
|
+/* Freescale PCIe doesn't support MSI in RC mode */
|
|
|
|
+static void quirk_fsl_no_msi(struct pci_dev *pdev)
|
|
|
|
+{
|
|
|
|
+ if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
|
|
|
|
+ pdev->no_msi = 1;
|
|
|
|
+}
|
|
|
|
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
|
|
|
|
--- a/include/linux/pci.h
|
|
|
|
+++ b/include/linux/pci.h
|
|
|
|
@@ -1944,6 +1944,7 @@ void pcibios_release_device(struct pci_d
|
|
|
|
void pcibios_penalize_isa_irq(int irq, int active);
|
|
|
|
int pcibios_alloc_irq(struct pci_dev *dev);
|
|
|
|
void pcibios_free_irq(struct pci_dev *dev);
|
|
|
|
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
|
|
|
|
|
|
|
|
#ifdef CONFIG_HIBERNATE_CALLBACKS
|
|
|
|
extern struct dev_pm_ops pcibios_pm_ops;
|