2024-04-09 22:33:05 +00:00
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From 0eb6bc551371070325b6606cc3bed6734ecad87d Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Fri, 1 Mar 2024 12:42:59 +0200
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Subject: [PATCH 39/48] net: dsa: mt7530: do not use SW_PHY_RST to reset MT7531
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switch
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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According to the document MT7531 Reference Manual for Development Board
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v1.0, the SW_PHY_RST bit on the SYS_CTRL register doesn't exist for
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MT7531. This is likely why forcing link down on all ports is necessary for
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MT7531.
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Therefore, do not set SW_PHY_RST on mt7531_setup().
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/dsa/mt7530.c | 6 ++----
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1 file changed, 2 insertions(+), 4 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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2024-04-29 15:09:24 +00:00
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@@ -2660,14 +2660,12 @@ mt7531_setup(struct dsa_switch *ds)
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2024-04-09 22:33:05 +00:00
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val = mt7530_read(priv, MT7531_TOP_SIG_SR);
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priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
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- /* all MACs must be forced link-down before sw reset */
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+ /* Force link down on all ports before internal reset */
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for (i = 0; i < MT7530_NUM_PORTS; i++)
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mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
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/* Reset the switch through internal reset */
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- mt7530_write(priv, MT7530_SYS_CTRL,
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- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
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- SYS_CTRL_REG_RST);
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+ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
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if (!priv->p5_sgmii) {
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mt7531_pll_setup(priv);
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