2024-03-01 01:56:57 +00:00
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From 1c09b694a1e9378931085e77d834a4d9786a5356 Mon Sep 17 00:00:00 2001
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From: Maso Huang <maso.huang@mediatek.com>
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Date: Thu, 7 Sep 2023 10:54:37 +0800
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Subject: [PATCH] arm64: dts: mt7986: add afe
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---
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arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 23 +++++++++++
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1 files changed, 23 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
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2024-05-02 19:40:57 +00:00
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@@ -202,6 +202,28 @@
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#interrupt-cells = <2>;
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2024-03-01 01:56:57 +00:00
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};
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+ afe: audio-controller@11210000 {
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+ compatible = "mediatek,mt7986-afe";
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+ reg = <0 0x11210000 0 0x9000>;
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+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
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+ <&infracfg CLK_INFRA_AUD_26M_CK>,
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+ <&infracfg CLK_INFRA_AUD_L_CK>,
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+ <&infracfg CLK_INFRA_AUD_AUD_CK>,
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+ <&infracfg CLK_INFRA_AUD_EG2_CK>;
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+ clock-names = "aud_bus_ck",
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+ "aud_26m_ck",
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+ "aud_l_ck",
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+ "aud_aud_ck",
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+ "aud_eg2_ck";
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+ assigned-clocks = <&topckgen CLK_TOP_A1SYS_SEL>,
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+ <&topckgen CLK_TOP_AUD_L_SEL>,
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+ <&topckgen CLK_TOP_A_TUNER_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_APLL2_D4>,
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+ <&apmixedsys CLK_APMIXED_APLL2>,
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+ <&topckgen CLK_TOP_APLL2_D4>;
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+ };
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+
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7986-pwm";
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reg = <0 0x10048000 0 0x1000>;
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