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58 lines
1.9 KiB
Diff
58 lines
1.9 KiB
Diff
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From ec198c390e1e111b912e1d244c0bca96a4f68945 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Fri, 5 Apr 2024 17:51:55 +0100
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Subject: [PATCH 1064/1085] drm/vc4: Ensure DSI is enabled for FIFO resets
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The block must be enabled for the FIFO resets to be actioned,
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so ensure this is the case.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 16 ++++++++--------
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1 file changed, 8 insertions(+), 8 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -408,7 +408,8 @@
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# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
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# define DSI0_CTRL_CTRL0 BIT(0)
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# define DSI1_CTRL_EN BIT(0)
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-# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
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+# define DSI0_CTRL_RESET_FIFOS (DSI0_CTRL_CTRL0 | \
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+ DSI_CTRL_CLR_LDF | \
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DSI0_CTRL_CLR_PBCF | \
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DSI0_CTRL_CLR_CPBCF | \
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DSI0_CTRL_CLR_PDF | \
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@@ -960,12 +961,17 @@ static void vc4_dsi_bridge_pre_enable(st
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hs_clock = clk_get_rate(dsi->pll_phy_clock);
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- /* Reset the DSI and all its fifos. */
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+ /*
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+ * Reset the DSI and all its fifos. The block must be enabled for the
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+ * FIFO resets to trigger.
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+ */
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DSI_PORT_WRITE(CTRL,
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DSI_CTRL_SOFT_RESET_CFG |
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DSI_PORT_BIT(CTRL_RESET_FIFOS));
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DSI_PORT_WRITE(CTRL,
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+ ((dsi->variant->port == 0) ?
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+ DSI0_CTRL_CTRL0 : DSI1_CTRL_EN) |
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DSI_CTRL_HSDT_EOT_DISABLE |
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DSI_CTRL_RX_LPDT_EOT_DISABLE);
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@@ -1133,12 +1139,6 @@ static void vc4_dsi_bridge_pre_enable(st
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DSI_DISP1_PFORMAT) |
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DSI_DISP1_ENABLE);
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- /* Ungate the block. */
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- if (dsi->variant->port == 0)
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- DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
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- else
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- DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
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-
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/* Bring AFE out of reset. */
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DSI_PORT_WRITE(PHY_AFEC0,
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DSI_PORT_READ(PHY_AFEC0) &
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