2022-07-25 00:31:20 +00:00
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From bc5e93e0cd22e360eda23859b939280205567580 Mon Sep 17 00:00:00 2001
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From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
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Date: Wed, 18 May 2022 15:54:42 +0100
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Subject: [PATCH 03/12] net: mtk_eth_soc: add mask and update PCS speed
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definitions
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The PCS speed setting is a two bit field, but it is defined as two
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separate bits. Add a bitfield mask for the speed definitions, an
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use the FIELD_PREP() macro to define each PCS speed.
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Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 +++++---
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1 file changed, 5 insertions(+), 3 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -17,6 +17,7 @@
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#include <linux/phylink.h>
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#include <linux/rhashtable.h>
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#include <linux/dim.h>
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+#include <linux/bitfield.h>
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#include "mtk_ppe.h"
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#define MTK_QDMA_PAGE_SIZE 2048
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2023-03-18 16:46:48 +00:00
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@@ -474,9 +475,10 @@
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2022-07-25 00:31:20 +00:00
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#define SGMSYS_SGMII_MODE 0x20
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#define SGMII_IF_MODE_BIT0 BIT(0)
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#define SGMII_SPEED_DUPLEX_AN BIT(1)
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-#define SGMII_SPEED_10 0x0
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-#define SGMII_SPEED_100 BIT(2)
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-#define SGMII_SPEED_1000 BIT(3)
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+#define SGMII_SPEED_MASK GENMASK(3, 2)
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+#define SGMII_SPEED_10 FIELD_PREP(SGMII_SPEED_MASK, 0)
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+#define SGMII_SPEED_100 FIELD_PREP(SGMII_SPEED_MASK, 1)
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+#define SGMII_SPEED_1000 FIELD_PREP(SGMII_SPEED_MASK, 2)
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#define SGMII_DUPLEX_FULL BIT(4)
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#define SGMII_IF_MODE_BIT5 BIT(5)
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#define SGMII_REMOTE_FAULT_DIS BIT(8)
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