2016-05-09 06:32:52 +00:00
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#include "mt7620a.dtsi"
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2013-10-08 21:10:15 +00:00
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/ {
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2019-07-03 21:22:02 +00:00
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compatible = "ralink,mt7620a-mt7530-evb", "ralink,mt7620a-soc";
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model = "Ralink MT7620a + MT7530 evaluation board";
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};
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2016-05-10 10:41:46 +00:00
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&spi0 {
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status = "okay";
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2020-05-07 14:15:27 +00:00
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flash@0 {
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compatible = "jedec,spi-nor";
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2016-05-14 17:22:08 +00:00
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reg = <0>;
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spi-max-frequency = <10000000>;
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2018-08-01 20:32:34 +00:00
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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2024-02-17 14:10:10 +00:00
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partition@40000 {
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2018-08-01 20:32:34 +00:00
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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2018-11-28 03:28:35 +00:00
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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2019-12-22 20:26:01 +00:00
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&state_default {
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gpio {
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2020-04-12 12:58:29 +00:00
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groups = "i2c", "uartf";
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function = "gpio";
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};
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};
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2016-05-10 10:41:46 +00:00
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
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2020-05-14 13:41:31 +00:00
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2016-05-10 10:41:46 +00:00
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mediatek,portmap = "llllw";
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port@5 {
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status = "okay";
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mediatek,fixed-link = <1000 1 1 1>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "rgmii";
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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phy-mode = "rgmii";
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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phy-mode = "rgmii";
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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phy-mode = "rgmii";
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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phy1f: ethernet-phy@1f {
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reg = <0x1f>;
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phy-mode = "rgmii";
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};
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2013-11-18 09:34:46 +00:00
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};
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2013-10-08 21:10:15 +00:00
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};
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2016-05-10 10:41:46 +00:00
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2021-04-03 18:42:51 +00:00
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&gsw {
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mediatek,ephy-base = /bits/ 8 <12>;
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};
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2016-05-10 10:41:46 +00:00
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&pcie {
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status = "okay";
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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