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36 lines
1.1 KiB
Diff
36 lines
1.1 KiB
Diff
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From 8e40644b272a4ddc9d3b58b4373dffcef02d1b63 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Tue, 4 Jun 2024 13:21:47 +0100
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Subject: [PATCH 1115/1135] mmc: sd: halt CQHCI before issuing a cache flush
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command
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SD cards perform cache flushes by a CMD49 extension register write -
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which needs to be started from the SDHCI command/argument registers and
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not a CQHCI slot.
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Host access to SD/CQ registers should be exclusive to one or the other,
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so issue a halt before doing the command.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/mmc/core/sd.c | 8 ++++++++
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1 file changed, 8 insertions(+)
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--- a/drivers/mmc/core/sd.c
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+++ b/drivers/mmc/core/sd.c
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@@ -1265,6 +1265,14 @@ static int sd_flush_cache(struct mmc_hos
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reg_buf = card->ext_reg_buf;
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/*
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+ * Flushing requires sending CMD49 (adtc), which can't be done as a DCMD
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+ * and conflicts with CQHCI - temporarily turn CQE off to use the SDHCI
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+ * command/argument registers.
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+ */
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+ if (host->cqe_on)
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+ host->cqe_ops->cqe_off(host);
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+
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+ /*
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* Set Flush Cache at bit 0 in the performance enhancement register at
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* 261 bytes offset.
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*/
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