2021-11-13 16:03:24 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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2024-02-07 13:48:43 +00:00
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#include <dt-bindings/leds/common.h>
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2021-11-13 16:03:24 +00:00
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#include <dt-bindings/mtd/partitions/uimage.h>
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/ {
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compatible = "humax,e10", "mediatek,mt7621-soc";
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model = "HUMAX E10";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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2022-07-05 22:20:32 +00:00
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label-mac-device = &gmac1;
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2021-11-13 16:03:24 +00:00
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};
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gpio-export {
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compatible = "gpio-export";
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gpio-usb-power {
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gpio-export,name = "power:usb";
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gpio-export,output = <1>;
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gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_GREEN>;
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2021-11-13 16:03:24 +00:00
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gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
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};
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pairing {
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label = "green:pairing";
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gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
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};
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wlan {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_WLAN;
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color = <LED_COLOR_ID_GREEN>;
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2021-11-13 16:03:24 +00:00
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gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
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};
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wps {
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2024-02-07 13:48:43 +00:00
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function = LED_FUNCTION_WPS;
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color = <LED_COLOR_ID_GREEN>;
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2021-11-13 16:03:24 +00:00
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gpios = <&gpio 12 GPIO_ACTIVE_HIGH>;
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};
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};
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keys {
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compatible = "gpio-keys";
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wps-reset {
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label = "wps_reset";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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2024-02-17 14:10:10 +00:00
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partition@40000 {
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2021-11-13 16:03:24 +00:00
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label = "factory";
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reg = <0x40000 0x30000>;
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read-only;
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x4da8>;
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};
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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eeprom_factory_8000: eeprom@8000 {
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reg = <0x8000 0x4da8>;
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};
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macaddr_factory_10007: macaddr@10007 {
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reg = <0x10007 0x6>;
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};
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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macaddr_factory_1000d: macaddr@1000d {
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reg = <0x1000d 0x6>;
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};
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2023-10-02 02:12:02 +00:00
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};
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};
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partition@70000 {
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compatible = "openwrt,uimage", "denx,uimage";
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openwrt,offset = <FW_EDIMAX_OFFSET>;
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openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
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label = "firmware";
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reg = <0x70000 0xf90000>;
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};
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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2023-10-02 02:12:02 +00:00
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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2021-11-13 16:03:24 +00:00
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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&pcie1 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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2023-10-02 02:12:02 +00:00
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nvmem-cells = <&eeprom_factory_8000>;
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nvmem-cell-names = "eeprom";
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2021-11-13 16:03:24 +00:00
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&gmac0 {
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nvmem-cells = <&macaddr_factory_10007>;
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nvmem-cell-names = "mac-address";
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};
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2022-07-05 22:20:32 +00:00
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy0>;
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nvmem-cells = <&macaddr_factory_1000d>;
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nvmem-cell-names = "mac-address";
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};
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ramips: mt7621-dts: describe switch PHYs and adjust PHY muxing
Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
bus the switch listens on. The PHY muxing feature makes use of this.
This is problematic as the PHY may be attached before the switch is
initialised, in which case, the PHY will fail to be attached.
Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
of switch MDIO bus") on mainline Linux, we can describe the switch PHYs on
the MDIO bus of the switch on the device tree.
When the PHY is described this way, the switch will be initialised first,
then the switch MDIO bus will be registered. Only after these steps, the
PHY will be attached.
Describe the switch PHYs on mt7621.dtsi and remove defining the switch PHY
on the SoC's mdio bus node. When the PHY muxing is in use, the interrupts
for the muxed PHY won't work, therefore delete the "interrupts" property on
the devices where the PHY muxing feature is in use.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
2024-04-28 19:52:51 +00:00
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ðphy0 {
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/delete-property/ interrupts;
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2022-07-05 22:20:32 +00:00
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};
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2021-11-13 16:03:24 +00:00
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&switch0 {
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ports {
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port@1 {
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status = "okay";
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label = "lan";
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};
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};
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};
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&state_default {
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gpio {
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groups = "jtag", "uart2", "uart3", "wdt";
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function = "gpio";
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};
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};
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