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106 lines
3.4 KiB
Diff
106 lines
3.4 KiB
Diff
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From f61d5d294f12df46380ef1af5f55abe8e8f45500 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Tue, 24 Oct 2023 16:20:42 +0100
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Subject: [PATCH 0713/1085] drm/vc4: crtc: Support odd horizontal timings on
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BCM2712
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BCM2711 runs pixelvalve at two pixels per clock cycle which results
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in an unfortunate limitation that odd horizontal timings are not
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possible. This is apparent on the standard DMT mode of 1366x768@60
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which cannot be driven with correct timing.
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BCM2712 defaults to the same behaviour, but has a mode to support
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odd timings. While internally it still runs at two pixels per clock,
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setting the PV_VCONTROL_ODD_TIMING bit makes it appear externally
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to behave as it is one pixel per clock.
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Switching to this mode fixes 1366x768@60 mode, and other custom
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resultions with odd horizontal timings.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 12 ++++--------
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drivers/gpu/drm/vc4/vc4_hdmi.c | 4 ++--
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drivers/gpu/drm/vc4/vc4_regs.h | 1 +
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3 files changed, 7 insertions(+), 10 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -399,12 +399,6 @@ static void vc4_crtc_config_pv(struct dr
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vc4_crtc_pixelvalve_reset(crtc);
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- /*
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- * NOTE: The BCM2712 has a H_OTE (Horizontal Odd Timing Enable)
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- * bit that, when set, will allow to specify the timings in
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- * pixels instead of cycles, thus allowing to specify odd
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- * timings.
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- */
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CRTC_WRITE(PV_HORZA,
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VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
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PV_HORZA_HBP) |
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@@ -449,6 +443,7 @@ static void vc4_crtc_config_pv(struct dr
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*/
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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+ (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
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(is_dsi ? PV_VCONTROL_DSI : 0) |
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PV_VCONTROL_INTERLACE |
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(odd_field_first
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@@ -460,6 +455,7 @@ static void vc4_crtc_config_pv(struct dr
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} else {
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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+ (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
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(is_dsi ? PV_VCONTROL_DSI : 0));
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CRTC_WRITE(PV_VSYNCD_EVEN, 0);
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}
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@@ -1332,7 +1328,7 @@ const struct vc4_pv_data bcm2712_pv0_dat
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.hvs_output = 0,
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},
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.fifo_depth = 64,
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- .pixels_per_clock = 2,
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+ .pixels_per_clock = 1,
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.encoder_types = {
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[0] = VC4_ENCODER_TYPE_HDMI0,
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},
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@@ -1345,7 +1341,7 @@ const struct vc4_pv_data bcm2712_pv1_dat
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.hvs_output = 1,
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},
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.fifo_depth = 64,
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- .pixels_per_clock = 2,
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+ .pixels_per_clock = 1,
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.encoder_types = {
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[0] = VC4_ENCODER_TYPE_HDMI1,
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},
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -3912,7 +3912,7 @@ static const struct vc4_hdmi_variant bcm
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PHY_LANE_2,
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PHY_LANE_CK,
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},
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- .unsupported_odd_h_timings = true,
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+ .unsupported_odd_h_timings = false,
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.external_irq_controller = true,
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.init_resources = vc5_hdmi_init_resources,
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@@ -3939,7 +3939,7 @@ static const struct vc4_hdmi_variant bcm
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PHY_LANE_2,
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PHY_LANE_CK,
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},
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- .unsupported_odd_h_timings = true,
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+ .unsupported_odd_h_timings = false,
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.external_irq_controller = true,
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.init_resources = vc5_hdmi_init_resources,
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -155,6 +155,7 @@
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# define PV_CONTROL_EN BIT(0)
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#define PV_V_CONTROL 0x04
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+# define PV_VCONTROL_ODD_TIMING BIT(29)
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# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
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# define PV_VCONTROL_ODD_DELAY_SHIFT 6
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# define PV_VCONTROL_ODD_FIRST BIT(5)
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