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53 lines
1.8 KiB
Diff
53 lines
1.8 KiB
Diff
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From 478b09fa2c00cbc40d25bc061befdf11f04a27ad Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Thu, 10 Feb 2022 10:48:58 +0100
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Subject: [PATCH 1/2] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
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Make system controller a reset provider for all the peripherals in the
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MT7621 SoC adding '#reset-cells' property.
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Acked-by: Rob Herring <robh@kernel.org>
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Acked-by: Stephen Boyd <sboyd@kernel.org>
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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.../devicetree/bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
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+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
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@@ -22,6 +22,11 @@ description: |
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The clocks are provided inside a system controller node.
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+ This node is also a reset provider for all the peripherals.
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+
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+ Reset related bits are defined in:
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+ [2]: <include/dt-bindings/reset/mt7621-reset.h>.
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+
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properties:
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compatible:
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items:
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@@ -37,6 +42,12 @@ properties:
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clocks.
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const: 1
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+ "#reset-cells":
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+ description:
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+ The first cell indicates the reset bit within the register, see
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+ [2] for available resets.
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+ const: 1
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+
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ralink,memctl:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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@@ -61,6 +72,7 @@ examples:
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compatible = "mediatek,mt7621-sysc", "syscon";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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+ #reset-cells = <1>;
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ralink,memctl = <&memc>;
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clock-output-names = "xtal", "cpu", "bus",
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"50m", "125m", "150m",
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