mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 00:11:13 +00:00
28 lines
860 B
Diff
28 lines
860 B
Diff
|
From a9913dccdeaabca37343d0d8b0a48cda1e434e02 Mon Sep 17 00:00:00 2001
|
||
|
From: Phil Elwell <phil@raspberrypi.org>
|
||
|
Date: Wed, 1 Mar 2017 16:06:53 +0000
|
||
|
Subject: [PATCH] clk-bcm2835: Correct the prediv logic
|
||
|
|
||
|
If a clock has the prediv flag set, both the integer and fractional
|
||
|
parts must be scaled when calculating the resulting frequency.
|
||
|
|
||
|
Signed-off-by: Phil Elwell <phil@raspberrypi.org>
|
||
|
---
|
||
|
drivers/clk/bcm/clk-bcm2835.c | 4 +++-
|
||
|
1 file changed, 3 insertions(+), 1 deletion(-)
|
||
|
|
||
|
--- a/drivers/clk/bcm/clk-bcm2835.c
|
||
|
+++ b/drivers/clk/bcm/clk-bcm2835.c
|
||
|
@@ -616,8 +616,10 @@ static unsigned long bcm2835_pll_get_rat
|
||
|
using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
|
||
|
data->ana->fb_prediv_mask;
|
||
|
|
||
|
- if (using_prediv)
|
||
|
+ if (using_prediv) {
|
||
|
ndiv *= 2;
|
||
|
+ fdiv *= 2;
|
||
|
+ }
|
||
|
|
||
|
return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
|
||
|
}
|