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61 lines
2.3 KiB
Diff
61 lines
2.3 KiB
Diff
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From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001
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From: Shawn Lin <shawn.lin@rock-chips.com>
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Date: Thu, 2 Feb 2023 08:35:16 +0800
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Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for
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rockchip platform
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For Rockchip platform, DLL bypass bit and start bit need to be set if
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DLL is not locked. And adjust pre-change delay to 0x3 for better signal
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test result.
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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++----
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1 file changed, 9 insertions(+), 4 deletions(-)
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--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
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+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -48,6 +48,7 @@
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#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
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#define DWCMSHC_EMMC_DLL_START_POINT 16
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#define DWCMSHC_EMMC_DLL_INC 8
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+#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
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#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
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#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
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#define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
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@@ -60,6 +61,7 @@
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#define DLL_RXCLK_NO_INVERTER 1
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#define DLL_RXCLK_INVERTER 0
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#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
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+#define DLL_RXCLK_ORI_GATE BIT(31)
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#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
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#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
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#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
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@@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str
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sdhci_writel(host, extra, reg);
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if (clock <= 52000000) {
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- /* Disable DLL and reset both of sample and drive clock */
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- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
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- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
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+ /*
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+ * Disable DLL and reset both of sample and drive clock.
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+ * The bypass bit and start bit need to be set if DLL is not locked.
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+ */
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+ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
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+ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
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sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
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sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
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/*
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@@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str
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}
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extra = 0x1 << 16 | /* tune clock stop en */
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- 0x2 << 17 | /* pre-change delay */
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+ 0x3 << 17 | /* pre-change delay */
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0x3 << 19; /* post-change delay */
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sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
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