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92 lines
2.5 KiB
Diff
92 lines
2.5 KiB
Diff
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From 8559b2db6aecbee62cf9e02c17349379d72edcfb Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Tue, 14 Mar 2023 21:24:35 +0800
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Subject: [PATCH 104/122] dt-bindings: watchdog: Add watchdog for StarFive
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JH7100 and JH7110
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Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC.
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And Use JH7100 as first StarFive SoC with watchdog.
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Guenter Roeck <linux@roeck-us.net>
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---
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.../watchdog/starfive,jh7100-wdt.yaml | 71 +++++++++++++++++++
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1 file changed, 71 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml
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@@ -0,0 +1,71 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive Watchdog for JH7100 and JH7110 SoC
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+
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+maintainers:
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+ - Xingyu Wu <xingyu.wu@starfivetech.com>
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+ - Samin Guo <samin.guo@starfivetech.com>
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+
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+description:
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+ The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog
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+ has only one timeout phase and reboots. And JH7110 watchdog has two
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+ timeout phases. At the first phase, the signal of watchdog interrupt
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+ output(WDOGINT) will rise when counter is 0. The counter will reload
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+ the timeout value. And then, if counter decreases to 0 again and WDOGINT
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+ isn't cleared, the watchdog will reset the system unless the watchdog
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+ reset is disabled.
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+
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+allOf:
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+ - $ref: watchdog.yaml#
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+
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+properties:
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+ compatible:
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+ enum:
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+ - starfive,jh7100-wdt
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+ - starfive,jh7110-wdt
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+
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+ reg:
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+ maxItems: 1
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+
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+ interrupts:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: APB clock
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+ - description: Core clock
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+
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+ clock-names:
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+ items:
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+ - const: apb
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+ - const: core
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+
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+ resets:
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+ items:
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+ - description: APB reset
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+ - description: Core reset
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ watchdog@12480000 {
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+ compatible = "starfive,jh7100-wdt";
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+ reg = <0x12480000 0x10000>;
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+ clocks = <&clk 171>,
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+ <&clk 172>;
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+ clock-names = "apb", "core";
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+ resets = <&rst 99>,
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+ <&rst 100>;
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+ };
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