mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
32 lines
992 B
Diff
32 lines
992 B
Diff
|
From b085b6233065b1e5145fbf93d75264b2042c0eb5 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Xingyu Wu <xingyu.wu@starfivetech.com>
|
||
|
|
Date: Tue, 14 Mar 2023 21:24:37 +0800
|
||
|
|
Subject: [PATCH 106/122] riscv: dts: starfive: jh7100: Add watchdog node
|
||
|
|
|
||
|
|
Add watchdog node for the StarFive JH7100 RISC-V SoC.
|
||
|
|
|
||
|
|
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
|
||
|
|
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
|
||
|
|
---
|
||
|
|
arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
|
||
|
|
1 file changed, 10 insertions(+)
|
||
|
|
|
||
|
|
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
|
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
||
|
|
@@ -238,5 +238,15 @@
|
||
|
|
#size-cells = <0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
+
|
||
|
|
+ watchdog@12480000 {
|
||
|
|
+ compatible = "starfive,jh7100-wdt";
|
||
|
|
+ reg = <0x0 0x12480000 0x0 0x10000>;
|
||
|
|
+ clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
|
||
|
|
+ <&clkgen JH7100_CLK_WDT_CORE>;
|
||
|
|
+ clock-names = "apb", "core";
|
||
|
|
+ resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
|
||
|
|
+ <&rstgen JH7100_RSTN_WDT>;
|
||
|
|
+ };
|
||
|
|
};
|
||
|
|
};
|