2022-01-10 01:12:45 +00:00
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From db305233136f5aa2444a8287a279384e8458c458 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Thu, 1 Apr 2021 20:12:48 +0200
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Subject: [PATCH] PCI: aardvark: Use separate INTA interrupt for emulated root
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bridge
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Emulated root bridge currently provides only one Legacy INTA interrupt
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which is used for reporting PCIe PME and ERR events and handled by kernel
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PCIe PME and AER drivers.
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Aardvark HW reports these PME and ERR events separately, so there is no
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need to mix real INTA interrupt and emulated INTA interrupt for PCIe PME
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and AER drivers.
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Register a new advk-RP (as in Root Port) irq chip and a new irq domain
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for emulated root bridge and use this new separate irq domain for
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providing INTA interrupt from emulated root bridge for PME and ERR events.
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The real INTA interrupt from real devices is now separate.
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A custom map_irq callback function on PCI host bridge structure is used to
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allocate IRQ mapping for emulated root bridge from new irq domain. Original
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callback of_irq_parse_and_map_pci() is used for all other devices as before.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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---
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drivers/pci/controller/pci-aardvark.c | 69 ++++++++++++++++++++++++++-
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1 file changed, 67 insertions(+), 2 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -280,6 +280,7 @@ struct advk_pcie {
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} wins[OB_WIN_COUNT];
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u8 wins_count;
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int irq;
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+ struct irq_domain *rp_irq_domain;
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struct irq_domain *irq_domain;
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struct irq_chip irq_chip;
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raw_spinlock_t irq_lock;
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2022-01-27 12:08:41 +00:00
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@@ -1443,6 +1444,44 @@ static void advk_pcie_remove_irq_domain(
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2022-01-10 01:12:45 +00:00
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irq_domain_remove(pcie->irq_domain);
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}
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+static struct irq_chip advk_rp_irq_chip = {
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+ .name = "advk-RP",
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+};
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+
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+static int advk_pcie_rp_irq_map(struct irq_domain *h,
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+ unsigned int virq, irq_hw_number_t hwirq)
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+{
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+ struct advk_pcie *pcie = h->host_data;
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+
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+ irq_set_chip_and_handler(virq, &advk_rp_irq_chip, handle_simple_irq);
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+ irq_set_chip_data(virq, pcie);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops advk_pcie_rp_irq_domain_ops = {
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+ .map = advk_pcie_rp_irq_map,
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+ .xlate = irq_domain_xlate_onecell,
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+};
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+
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+static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie)
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+{
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+ pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1,
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+ &advk_pcie_rp_irq_domain_ops,
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+ pcie);
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+ if (!pcie->rp_irq_domain) {
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+ dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n");
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+ return -ENOMEM;
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+ }
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+
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+ return 0;
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+}
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+
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+static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie)
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+{
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+ irq_domain_remove(pcie->rp_irq_domain);
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+}
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+
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static void advk_pcie_handle_pme(struct advk_pcie *pcie)
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{
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u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;
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2022-01-27 12:08:41 +00:00
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@@ -1465,7 +1504,7 @@ static void advk_pcie_handle_pme(struct
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2022-01-10 01:12:45 +00:00
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if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))
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return;
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- virq = irq_find_mapping(pcie->irq_domain, 0);
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+ virq = irq_find_mapping(pcie->rp_irq_domain, 0);
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if (generic_handle_irq(virq) == -EINVAL)
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dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n");
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}
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2022-01-27 12:08:41 +00:00
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@@ -1522,7 +1561,7 @@ static void advk_pcie_handle_int(struct
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2022-01-10 01:12:45 +00:00
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* Aardvark HW returns zero for PCI_ERR_ROOT_AER_IRQ, so use
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* PCIe interrupt 0
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*/
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- virq = irq_find_mapping(pcie->irq_domain, 0);
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+ virq = irq_find_mapping(pcie->rp_irq_domain, 0);
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if (generic_handle_irq(virq) == -EINVAL)
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dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n");
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}
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2022-01-27 12:08:41 +00:00
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@@ -1568,6 +1607,21 @@ static void advk_pcie_irq_handler(struct
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2022-01-10 01:12:45 +00:00
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chained_irq_exit(chip, desc);
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}
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+static int advk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ struct advk_pcie *pcie = dev->bus->sysdata;
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+
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+ /*
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+ * Emulated root bridge has its own emulated irq chip and irq domain.
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+ * Argument pin is the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD) and
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+ * hwirq for irq_create_mapping() is indexed from zero.
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+ */
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+ if (pci_is_root_bus(dev->bus))
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+ return irq_create_mapping(pcie->rp_irq_domain, pin - 1);
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+ else
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+ return of_irq_parse_and_map_pci(dev, slot, pin);
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+}
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+
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static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)
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{
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phy_power_off(pcie->phy);
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2022-01-27 12:08:41 +00:00
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@@ -1771,14 +1825,24 @@ static int advk_pcie_probe(struct platfo
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2022-01-10 01:12:45 +00:00
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return ret;
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}
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+ ret = advk_pcie_init_rp_irq_domain(pcie);
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+ if (ret) {
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+ dev_err(dev, "Failed to initialize irq\n");
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+ advk_pcie_remove_msi_irq_domain(pcie);
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+ advk_pcie_remove_irq_domain(pcie);
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+ return ret;
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+ }
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+
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irq_set_chained_handler_and_data(pcie->irq, advk_pcie_irq_handler, pcie);
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bridge->sysdata = pcie;
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bridge->ops = &advk_pcie_ops;
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+ bridge->map_irq = advk_pcie_map_irq;
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ret = pci_host_probe(bridge);
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if (ret < 0) {
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irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
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+ advk_pcie_remove_rp_irq_domain(pcie);
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advk_pcie_remove_msi_irq_domain(pcie);
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advk_pcie_remove_irq_domain(pcie);
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return ret;
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2022-01-27 12:08:41 +00:00
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@@ -1830,6 +1894,7 @@ static int advk_pcie_remove(struct platf
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2022-01-10 01:12:45 +00:00
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irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
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/* Remove IRQ domains */
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+ advk_pcie_remove_rp_irq_domain(pcie);
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advk_pcie_remove_msi_irq_domain(pcie);
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advk_pcie_remove_irq_domain(pcie);
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