2021-11-18 15:34:55 +00:00
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From 6e238362b9793bf334c9bed2291b571cbbc75b0b Mon Sep 17 00:00:00 2001
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2020-09-12 20:28:38 +00:00
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From: Florian Fainelli <f.fainelli@gmail.com>
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2021-11-18 15:34:55 +00:00
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Date: Wed, 27 Oct 2021 12:37:29 -0700
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2020-09-12 20:28:38 +00:00
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Subject: [PATCH] ARM: dts: BCM5301X: Fix I2C controller interrupt
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The I2C interrupt controller line is off by 32 because the datasheet
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describes interrupt inputs into the GIC which are for Shared Peripheral
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Interrupts and are starting at offset 32. The ARM GIC binding expects
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the SPI interrupts to be numbered from 0 relative to the SPI base.
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Fixes: bb097e3e0045 ("ARM: dts: BCM5301X: Add I2C support to the DT")
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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2021-11-18 15:34:55 +00:00
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Tested-by: Christian Lamparter <chunkeey@gmail.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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2020-09-12 20:28:38 +00:00
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---
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arch/arm/boot/dts/bcm5301x.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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2021-11-04 06:00:21 +00:00
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@@ -408,7 +408,7 @@
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2020-09-12 20:28:38 +00:00
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i2c0: i2c@18009000 {
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compatible = "brcm,iproc-i2c";
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reg = <0x18009000 0x50>;
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- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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