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100 lines
3.0 KiB
Diff
100 lines
3.0 KiB
Diff
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From 6470986f037880ce76960c369d6e5a5270e7ce32 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Sun, 10 Mar 2024 15:39:07 +0000
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Subject: [PATCH 2/3] mediatek: snfi: adjust pin drive strength for Fidelix
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SPI-NAND
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It seems like we might need to adjust the pin driver strength to 12mA
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for Fidelix SPI-NAND chip on MT7622 to avoid SPI data corruption on
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some devices.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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.../apsoc_common/drivers/snfi/mtk-snand-def.h | 7 +++++
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.../apsoc_common/drivers/snfi/mtk-snand-ids.c | 4 ++-
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.../apsoc_common/drivers/snfi/mtk-snand.c | 30 +++++++++++++++++++
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3 files changed, 40 insertions(+), 1 deletion(-)
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--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
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+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-def.h
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@@ -86,6 +86,12 @@ struct snand_mem_org {
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typedef int (*snand_select_die_t)(struct mtk_snand *snf, uint32_t dieidx);
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+enum snand_drv {
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+ SNAND_DRV_NO_CHANGE = 0,
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+ SNAND_DRV_8mA = 8,
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+ SNAND_DRV_12mA = 12,
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+};
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+
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struct snand_flash_info {
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const char *model;
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struct snand_id id;
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@@ -93,6 +99,7 @@ struct snand_flash_info {
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const struct snand_io_cap *cap_rd;
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const struct snand_io_cap *cap_pl;
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snand_select_die_t select_die;
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+ enum snand_drv drv;
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};
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#define SNAND_INFO(_model, _id, _memorg, _cap_rd, _cap_pl, ...) \
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--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
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+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand-ids.c
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@@ -424,7 +424,9 @@ static const struct snand_flash_info sna
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SNAND_INFO("FM35Q1GA", SNAND_ID(SNAND_ID_DYMMY, 0xe5, 0x71),
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SNAND_MEMORG_1G_2K_64,
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&snand_cap_read_from_cache_x4_only,
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- &snand_cap_program_load_x4),
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+ &snand_cap_program_load_x4,
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+ NULL,
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+ SNAND_DRV_12mA),
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SNAND_INFO("PN26G01A", SNAND_ID(SNAND_ID_DYMMY, 0xa1, 0xe1),
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SNAND_MEMORG_1G_2K_128,
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--- a/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
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+++ b/plat/mediatek/apsoc_common/drivers/snfi/mtk-snand.c
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@@ -1845,6 +1845,33 @@ static int mtk_snand_id_probe(struct mtk
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return -EINVAL;
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}
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+#define MT7622_GPIO_BASE (void *)0x10211000
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+#define MT7622_GPIO_DRIV(x) (MT7622_GPIO_BASE + 0x900 + 0x10 * x)
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+
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+void mtk_mt7622_snand_adjust_drive(void *dev, enum snand_drv drv)
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+{
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+ uint32_t e4, e8;
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+
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+ e4 = readl(MT7622_GPIO_DRIV(6)) & ~(0x3f00);
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+ e8 = readl(MT7622_GPIO_DRIV(7)) & ~(0x3f00);
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+
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+ switch (drv) {
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+ case SNAND_DRV_8mA:
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+ e4 |= 0x3f00;
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+ break;
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+ case SNAND_DRV_12mA:
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+ e8 |= 0x3f00;
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+ break;
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+ default:
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+ return;
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+ }
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+
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+ snand_log_chip(dev, "adjusting SPI-NAND pin drive strength to %umA\n", drv);
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+
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+ writel(e4, MT7622_GPIO_DRIV(6));
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+ writel(e8, MT7622_GPIO_DRIV(7));
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+}
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+
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int mtk_snand_init(void *dev, const struct mtk_snand_platdata *pdata,
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struct mtk_snand **psnf)
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{
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@@ -1888,6 +1915,9 @@ int mtk_snand_init(void *dev, const stru
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if (ret)
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return ret;
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+ if (pdata->soc == SNAND_SOC_MT7622 && snand_info->drv)
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+ mtk_mt7622_snand_adjust_drive(dev, snand_info->drv);
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+
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rawpage_size = snand_info->memorg.pagesize +
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snand_info->memorg.sparesize;
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