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https://github.com/openwrt/openwrt.git
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76 lines
2.6 KiB
Diff
76 lines
2.6 KiB
Diff
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From 1f788a0a5092b1e1cfd02aa7f31ceb551befa7e6 Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Tue, 14 Mar 2023 16:43:50 +0800
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Subject: [PATCH 033/122] dt-bindings: clock: jh7110-syscrg: Add PLL clock
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inputs
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Add PLL clock inputs from PLL clock generator.
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Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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.../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++--
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1 file changed, 18 insertions(+), 2 deletions(-)
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--- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
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+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
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@@ -27,6 +27,9 @@ properties:
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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+ - description: PLL0
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+ - description: PLL1
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+ - description: PLL2
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- items:
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- description: Main Oscillator (24 MHz)
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@@ -38,6 +41,9 @@ properties:
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- description: External I2S RX left/right channel clock
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- description: External TDM clock
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- description: External audio master clock
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+ - description: PLL0
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+ - description: PLL1
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+ - description: PLL2
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clock-names:
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oneOf:
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@@ -52,6 +58,9 @@ properties:
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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+ - const: pll0_out
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+ - const: pll1_out
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+ - const: pll2_out
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- items:
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- const: osc
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@@ -63,6 +72,9 @@ properties:
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- const: i2srx_lrck_ext
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- const: tdm_ext
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- const: mclk_ext
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+ - const: pll0_out
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+ - const: pll1_out
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+ - const: pll2_out
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'#clock-cells':
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const: 1
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@@ -93,12 +105,16 @@ examples:
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<&gmac1_rgmii_rxin>,
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<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
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<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
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- <&tdm_ext>, <&mclk_ext>;
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+ <&tdm_ext>, <&mclk_ext>,
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+ <&pllclk JH7110_CLK_PLL0_OUT>,
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+ <&pllclk JH7110_CLK_PLL1_OUT>,
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+ <&pllclk JH7110_CLK_PLL2_OUT>;
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clock-names = "osc", "gmac1_rmii_refin",
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"gmac1_rgmii_rxin",
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"i2stx_bclk_ext", "i2stx_lrck_ext",
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"i2srx_bclk_ext", "i2srx_lrck_ext",
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- "tdm_ext", "mclk_ext";
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+ "tdm_ext", "mclk_ext",
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+ "pll0_out", "pll1_out", "pll2_out";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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