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72 lines
2.7 KiB
Diff
72 lines
2.7 KiB
Diff
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From 7d4de40b3262cfb0f9657c811a981ed8d4119b96 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Wed, 20 Sep 2023 13:01:11 +0100
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Subject: [PATCH 0697/1085] drivers: pci: brcmstb: optionally extend Tperst_clk
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time during link-up
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The RC has a feature that allows for manual control over the deassertion
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of the PERST# output pin, which allows the time between refclk active
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and reset deassert at the EP to be increased.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/pci/controller/pcie-brcmstb.c | 24 +++++++++++++++++++++++-
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1 file changed, 23 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -140,6 +140,7 @@
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG pcie->reg_offsets[PCIE_HARD_DEBUG]
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
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+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK 0x8
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
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#define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
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#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK 0x00200000
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@@ -354,6 +355,7 @@ struct brcm_pcie {
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bool (*rc_mode)(struct brcm_pcie *pcie);
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struct subdev_regulators *sr;
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bool ep_wakeup_capable;
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+ u32 tperst_clk_ms;
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};
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static inline bool is_bmips(const struct brcm_pcie *pcie)
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@@ -1386,9 +1388,28 @@ static int brcm_pcie_start_link(struct b
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u16 nlw, cls, lnksta;
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bool ssc_good = false;
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int ret, i;
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+ u32 tmp;
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/* Unassert the fundamental reset */
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- pcie->perst_set(pcie, 0);
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+ if (pcie->tperst_clk_ms) {
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+ /*
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+ * Increase Tperst_clk time by forcing PERST# output low while
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+ * the internal reset is released, so the PLL generates stable
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+ * refclk output further in advance of PERST# deassertion.
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+ */
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+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
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+ u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK);
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+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
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+
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+ pcie->perst_set(pcie, 0);
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+ msleep(pcie->tperst_clk_ms);
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+
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+ tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
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+ u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK);
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+ writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
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+ } else {
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+ pcie->perst_set(pcie, 0);
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+ }
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/*
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* Wait for 100ms after PERST# deassertion; see PCIe CEM specification
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@@ -1919,6 +1940,7 @@ static int brcm_pcie_probe(struct platfo
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pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
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pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss");
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pcie->rcb_mps_mode = of_property_read_bool(np, "brcm,enable-mps-rcb");
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+ of_property_read_u32(np, "brcm,tperst-clk-ms", &pcie->tperst_clk_ms);
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ret = clk_prepare_enable(pcie->clk);
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if (ret) {
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