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106 lines
2.8 KiB
Diff
106 lines
2.8 KiB
Diff
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From 574824623507b463be88194987f54ccb6c3b8ce4 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Mon, 20 May 2024 15:12:41 +0100
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Subject: [PATCH 1097/1135] DTS: overlays: add pciex1-compat-pi5
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Interop testing with the M.2 HAT has revealed that there are many quirky
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endpoint devices out there, so users should have a way of rapidly
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iterating to find which quirk is causing reliability issues.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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arch/arm/boot/dts/overlays/Makefile | 1 +
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arch/arm/boot/dts/overlays/README | 12 ++++++
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arch/arm/boot/dts/overlays/overlay_map.dts | 4 ++
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.../overlays/pciex1-compat-pi5-overlay.dts | 40 +++++++++++++++++++
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4 files changed, 57 insertions(+)
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create mode 100644 arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
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--- a/arch/arm/boot/dts/overlays/Makefile
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+++ b/arch/arm/boot/dts/overlays/Makefile
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@@ -189,6 +189,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
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pcf857x.dtbo \
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pcie-32bit-dma.dtbo \
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pcie-32bit-dma-pi5.dtbo \
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+ pciex1-compat-pi5.dtbo \
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pibell.dtbo \
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pifacedigital.dtbo \
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pifi-40.dtbo \
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--- a/arch/arm/boot/dts/overlays/README
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+++ b/arch/arm/boot/dts/overlays/README
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@@ -3540,6 +3540,18 @@ Info: Force PCIe config to support 32b
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Load: dtoverlay=pcie-32bit-dma-pi5
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Params: <None>
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+
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+Name: pciex1-compat-pi5
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+Info: Compatibility features for pciex1 on Pi 5.
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+Load: dtoverlay=pciex1-compat-pi5,<param>=<val>
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+Params: l1ss Enable ASPM L1 sub-state support
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+ no-l0s Disable ASPM L0s
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+ no-mip Revert to the MSI target in the RC, instead of
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+ the MSI-MIP peripheral. Use if a) more than 8
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+ interrupt vectors are required or b) the EP
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+ requires DMA and MSI addresses to be 32bit.
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+
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+
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[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ]
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--- a/arch/arm/boot/dts/overlays/overlay_map.dts
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+++ b/arch/arm/boot/dts/overlays/overlay_map.dts
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@@ -196,6 +196,10 @@
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bcm2712;
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};
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+ pcie-compat-pi5 {
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+ bcm2712;
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+ };
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+
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pi3-act-led {
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renamed = "act-led";
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};
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlays/pciex1-compat-pi5-overlay.dts
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@@ -0,0 +1,40 @@
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+/*
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+ * Various feature switches for the 1-lane PCIe controller on Pi 5
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+ */
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+
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "brcm,bcm2712";
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+
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+ /* Enable L1 sub-state support */
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+ fragment@0 {
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+ target = <&pciex1>;
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+ __dormant__ {
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+ brcm,enable-l1ss;
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+ };
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+ };
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+
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+ /* Disable ASPM L0s */
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+ fragment@1 {
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+ target = <&pciex1>;
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+ __dormant__ {
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+ aspm-no-l0s;
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+ };
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+ };
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+
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+ /* Use RC MSI target instead of MIP MSIx target */
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+ fragment@2 {
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+ target = <&pciex1>;
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+ __dormant__ {
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+ msi-parent = <&pciex1>;
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+ };
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+ };
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+
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+ __overrides__ {
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+ l1ss = <0>, "+0";
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+ no-l0s = <0>, "+1";
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+ no-mip = <0>, "+2";
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+ };
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+};
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