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openwrt/target/linux/layerscape/patches-4.4/8233-i2c-pca954x-Add-option-to-skip-disabling-PCA954x-Mux.patch

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layerscape: add ls2088ardb device support The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
From a4be9046c3a3fc39a06089553df8cc19a2abd814 Mon Sep 17 00:00:00 2001
From: Priyanka Jain <Priyanka.Jain@freescale.com>
Date: Tue, 3 Nov 2015 11:25:24 +0530
Subject: [PATCH 233/238] i2c: pca954x: Add option to skip disabling PCA954x
Mux device
On some Layerscape boards like LS2085ARDB/LS2080ARDB,
input pull-up resistors on PCA954x Mux device are
missing on board. So, if mux are disabled after powered-on,
input lines will float leading to incorrect functionality.
Hence, PCA954x Mux device should never be turned-off after
power-on.
Add option to skip disabling PCA954x Mux device
if device tree contians "i2c-mux-never-disable" property
for pca954x device node.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
---
drivers/i2c/muxes/i2c-mux-pca954x.c | 38 +++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -63,6 +63,7 @@ struct pca954x {
struct i2c_adapter *virt_adaps[PCA954X_MAX_NCHANS];
u8 last_chan; /* last register value */
+ u8 disable_mux; /* do not disable mux if val not 0 */
};
struct chip_desc {
kernel: bump to 4.4.40 Refresh patches on all 4.4 supported platforms. Compile & run tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2017-01-06 12:53:27 +00:00
@@ -174,6 +175,13 @@ static int pca954x_deselect_mux(struct i
layerscape: add ls2088ardb device support The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
{
struct pca954x *data = i2c_get_clientdata(client);
+#ifdef CONFIG_ARCH_LAYERSCAPE
+ if (data->disable_mux != 0)
+ data->last_chan = chips[data->type].nchans;
+ else
+ data->last_chan = 0;
+ return pca954x_reg_write(adap, client, data->disable_mux);
+#endif
/* Deselect active channel */
data->last_chan = 0;
return pca954x_reg_write(adap, client, data->last_chan);
kernel: bump to 4.4.40 Refresh patches on all 4.4 supported platforms. Compile & run tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2017-01-06 12:53:27 +00:00
@@ -201,6 +209,23 @@ static int pca954x_probe(struct i2c_clie
layerscape: add ls2088ardb device support The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
if (!data)
return -ENOMEM;
+#ifdef CONFIG_ARCH_LAYERSCAPE
+ /* The point here is that you must not disable a mux if there
+ * are no pullups on the input or you mess up the I2C. This
+ * needs to be put into the DTS really as the kernel cannot
+ * know this otherwise.
+ */
+ data->type = id->driver_data;
+ data->disable_mux = of_node &&
+ of_property_read_bool(of_node, "i2c-mux-never-disable") &&
+ chips[data->type].muxtype == pca954x_ismux ?
+ chips[data->type].enable : 0;
+ /* force the first selection */
+ if (data->disable_mux != 0)
+ data->last_chan = chips[data->type].nchans;
+ else
+ data->last_chan = 0;
+#endif
i2c_set_clientdata(client, data);
/* Get the mux out of reset if a reset GPIO is specified. */
kernel: bump to 4.4.40 Refresh patches on all 4.4 supported platforms. Compile & run tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2017-01-06 12:53:27 +00:00
@@ -212,13 +237,19 @@ static int pca954x_probe(struct i2c_clie
layerscape: add ls2088ardb device support The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
* that the mux is in fact present. This also
* initializes the mux to disconnected state.
*/
+#ifdef CONFIG_ARCH_LAYERSCAPE
+ if (i2c_smbus_write_byte(client, data->disable_mux) < 0) {
+#else
if (i2c_smbus_write_byte(client, 0) < 0) {
+#endif
dev_warn(&client->dev, "probe failed\n");
return -ENODEV;
}
+#ifndef CONFIG_ARCH_LAYERSCAPE
data->type = id->driver_data;
data->last_chan = 0; /* force the first selection */
+#endif
idle_disconnect_dt = of_node &&
of_property_read_bool(of_node, "i2c-mux-idle-disconnect");
kernel: bump to 4.4.40 Refresh patches on all 4.4 supported platforms. Compile & run tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2017-01-06 12:53:27 +00:00
@@ -289,6 +320,13 @@ static int pca954x_resume(struct device
layerscape: add ls2088ardb device support The QorIQ LS2088A processor is built on the Layerscape architecture combining eight ARM A72 processor cores with advanced, high-performance datapath acceleration and network, peripheral interfaces required for networking, telecom, wireless infrastructure, aerospace applications and general-purpose embedded applications. Features summary: - Eight 64-bit ARM v8 Cortex-A72 CPUs - Two 64-bit DDR4 SDRAM memory controller with ECC - One 32-bit DDR3 SDRAM memory controller with ECC - Data path acceleration architecture 2.0 (DPAA2) - Ethernet interfaces - IFC, 4 PCIe, 2 SATA, 2 USB, 1 SDXC, 2 DUARTs etc Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
2016-12-27 17:28:02 +00:00
struct i2c_client *client = to_i2c_client(dev);
struct pca954x *data = i2c_get_clientdata(client);
+#ifdef CONFIG_ARCH_LAYERSCAPE
+ if (data->disable_mux != 0)
+ data->last_chan = chips[data->type].nchans;
+ else
+ data->last_chan = 0;
+ return i2c_smbus_write_byte(client, data->disable_mux);
+#endif
data->last_chan = 0;
return i2c_smbus_write_byte(client, 0);
}
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