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88 lines
2.7 KiB
Diff
88 lines
2.7 KiB
Diff
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From 5c315652c1b43a6a3abe48c2842cde822ac0ff3c Mon Sep 17 00:00:00 2001
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From: Yunhui Cui <B56489@freescale.com>
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Date: Wed, 20 Jan 2016 18:40:31 +0800
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Subject: [PATCH 097/113] mtd:fsl-quadspi:use the property fields of SPI-NOR
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We can get the read/write/erase opcode from the spi nor framework
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directly. This patch uses the information stored in the SPI-NOR to
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remove the hardcode in the fsl_qspi_init_lut().
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Signed-off-by: Yunhui Cui <B56489@freescale.com>
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---
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drivers/mtd/spi-nor/fsl-quadspi.c | 40 +++++++++++--------------------------
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1 file changed, 12 insertions(+), 28 deletions(-)
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--- a/drivers/mtd/spi-nor/fsl-quadspi.c
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+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
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@@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl
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void __iomem *base = q->iobase;
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int rxfifo = q->devtype_data->rxfifo;
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u32 lut_base;
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- u8 cmd, addrlen, dummy;
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int i;
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+ struct spi_nor *nor = &q->nor[0];
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+ u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
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+ u8 read_op = nor->read_opcode;
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+ u8 read_dm = nor->read_dummy;
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+
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fsl_qspi_unlock_lut(q);
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/* Clear all the LUT table */
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@@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl
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/* Quad Read */
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lut_base = SEQID_QUAD_READ * 4;
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- if (q->nor_size <= SZ_16M) {
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- cmd = SPINOR_OP_READ_1_1_4;
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- addrlen = ADDR24BIT;
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- dummy = 8;
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- } else {
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- /* use the 4-byte address */
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- cmd = SPINOR_OP_READ_1_1_4;
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- addrlen = ADDR32BIT;
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- dummy = 8;
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- }
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-
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- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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- qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
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+ qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
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+ LUT1(FSL_READ, PAD4, rxfifo),
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base + QUADSPI_LUT(lut_base + 1));
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/* Write enable */
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@@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl
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/* Page Program */
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lut_base = SEQID_PP * 4;
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- if (q->nor_size <= SZ_16M) {
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- cmd = SPINOR_OP_PP;
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- addrlen = ADDR24BIT;
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- } else {
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- /* use the 4-byte address */
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- cmd = SPINOR_OP_PP;
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- addrlen = ADDR32BIT;
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- }
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-
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- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
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+ LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
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base + QUADSPI_LUT(lut_base + 1));
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@@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl
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/* Erase a sector */
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lut_base = SEQID_SE * 4;
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- cmd = q->nor[0].erase_opcode;
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- addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
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-
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- qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
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+ qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
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+ LUT1(ADDR, PAD1, addrlen),
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base + QUADSPI_LUT(lut_base));
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/* Erase the whole chip */
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