openwrt/target/linux/ramips/dts/mt7620a_planex_mzk-750dhp.dts

/dts-v1/;

#include "mt7620a.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	compatible = "planex,mzk-750dhp", "ralink,mt7620a-soc";
	model = "Planex MZK-750DHP";

	aliases {
		led-boot = &led_power;
		led-failsafe = &led_power;
		led-running = &led_power;
		led-upgrade = &led_power;
	};

	leds {
		compatible = "gpio-leds";

		wps {
			label = "mzk-750dhp:green:wps";
			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
		};

		led_power: power {
			label = "mzk-750dhp:green:power";
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};

		wlan5g {
			label = "mzk-750dhp:green:wlan5g";
			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
		};
	};

	keys {
		compatible = "gpio-keys-polled";
		poll-interval = <20>;

		s1 {
			label = "reset";
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};

		s2 {
			label = "wps";
			gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WPS_BUTTON>;
		};
	};
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&spi0 {
	status = "okay";

	m25p80@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x30000>;
				read-only;
			};

			partition@30000 {
				label = "u-boot-env";
				reg = <0x30000 0x10000>;
				read-only;
			};

			factory: partition@40000 {
				label = "factory";
				reg = <0x40000 0x10000>;
				read-only;
			};

			partition@50000 {
				compatible = "denx,uimage";
				label = "firmware";
				reg = <0x50000 0x7b0000>;
			};
		};
	};
};

&pinctrl {
	state_default: pinctrl0 {
		gpio {
			ralink,group = "i2c", "spi refclk", "rgmii1", "nd_sd";
			ralink,function = "gpio";
		};
	};
};

&ethernet {
	pinctrl-names = "default";
	pinctrl-0 = <&ephy_pins>;
	mtd-mac-address = <&factory 0x4>;
	mediatek,portmap = "llllw";
};

&gsw {
	mediatek,port4 = "ephy";
};

&wmac {
	ralink,mtd-eeprom = <&factory 0>;
};

&pcie {
	status = "okay";
};

&pcie0 {
	mt76@0,0 {
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x8000>;
	};
};