2020-03-01 09:01:09 +00:00
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--- a/arch/mips/pci/pci-mt7620.c
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+++ b/arch/mips/pci/pci-mt7620.c
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2020-03-01 09:06:45 +00:00
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@@ -32,6 +32,7 @@
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2020-03-01 09:01:09 +00:00
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#define PPLL_CFG1 0x9c
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#define PPLL_DRV 0xa0
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2020-03-01 09:06:45 +00:00
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+#define PPLL_LD BIT(23)
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#define PDRV_SW_SET BIT(31)
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#define LC_CKDRVPD BIT(19)
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#define LC_CKDRVOHZ BIT(18)
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@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla
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2020-03-01 09:01:09 +00:00
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rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
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mdelay(100);
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- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
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- dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
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+ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
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+ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n");
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reset_control_assert(rstpcie0);
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rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
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return -1;
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