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53 lines
1.8 KiB
Diff
53 lines
1.8 KiB
Diff
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From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Wed, 30 Mar 2022 21:24:21 -0500
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Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI
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D1's HDMI controller contains some platform integration changes.
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It now has no external TMDS clock. The controller also supports HDCP
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without an external clock or reset.
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While the maximum HDMI frequency is not explicity stated, the BSP PHY
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driver provides PLL configurations only up to 297 MHz, so use that as
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the max frequency.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++-
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1 file changed, 10 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
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@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev
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return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl),
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"Could not get ctrl reset control\n");
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- hdmi->clk_tmds = devm_clk_get(dev, "tmds");
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+ hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds");
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if (IS_ERR(hdmi->clk_tmds))
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return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds),
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"Couldn't get the tmds clock\n");
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@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks
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.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
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};
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+static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = {
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+ .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
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+ .use_drm_infoframe = true,
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+};
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+
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static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
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.mode_valid = sun8i_dw_hdmi_mode_valid_h6,
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.use_drm_infoframe = true,
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@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d
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.data = &sun8i_a83t_quirks,
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},
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{
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+ .compatible = "allwinner,sun20i-d1-dw-hdmi",
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+ .data = &sun20i_d1_quirks,
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+ },
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+ {
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.compatible = "allwinner,sun50i-h6-dw-hdmi",
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.data = &sun50i_h6_quirks,
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},
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