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28 lines
849 B
C
28 lines
849 B
C
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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#ifndef __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_CLK_H
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#define __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_CLK_H
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#define CLK_PLL_CPU 0
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#define CLK_PLL_DDR 1
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#define CLK_PLL_CMN 2
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#define CLK_MUXDIV_BUS1 3
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#define CLK_MUXDIV_BUS2 4
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#define CLK_MUXDIV_BUS3 5
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#define CLK_MUXDIV_CPU 6
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#define CLK_MUXDIV_PBUS 7
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#define CLK_MUXDIV_MEM_PHY 8
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#define CLK_MUXDIV_UART 9
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#define CLK_MUXDIV_ETH_REF 10
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#define CLK_MUXDIV_ETH_BYP_REF 11
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#define CLK_MUXDIV_ETH_TSU 12
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#define CLK_MUXDIV_GMAC_BYP_REF 13
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#define CLK_MUXDIV_M6250_0 14
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#define CLK_MUXDIV_M6250_1 15
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#define CLK_MUXDIV_WLAN24_PLF 16
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#define CLK_MUXDIV_WLAN5_PLF 17
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#define CLK_MUXDIV_USBPHY_REF 18
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#define CLK_MUXDIV_TCLK 19
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#define CLK_MUXDIV_NPU_PE_CLK 20
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#define CLK_SF19A2890_MAX 21
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#endif /* __DT_BINDINGS_CLOCK_SIFLOWER_SF19A2890_CLK_H */
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