openwrt/target/linux/ath79/dts/qca9558_engenius_esr900.dts

86 lines
1.5 KiB
Plaintext
Raw Normal View History

ath79: add support for Senao Engenius ESR900 FCC ID: A8J-ESR900 Engenius ESR900 is an indoor wireless router with a gigabit ethernet switch, dual-band wireless, internal antenna plates, and a USB 2.0 port **Specification:** - QCA9558 SOC 2.4 GHz, 3x3 - AR9580 WLAN PCIe on board, 5 GHz, 3x3 - AR8327N SW 4 ports LAN, 1 port WAN - 40 MHz clock - 16 MB FLASH MX25L12845EMI-10G - 2x 64 MB RAM - UART at J1 populated, RX grounded - 6 internal antenna plates (omni-directional) - 5 LEDs, 1 button (power, 2G, 5G, WAN, WPS) (reset) **MAC addresses:** Base MAC address labeled as "MAC ADDRESS" MAC "wanaddr" is not similar to "ethaddr" eth0 *:06 MAC u-boot-env ethaddr phy0 *:06 MAC u-boot-env ethaddr phy1 *:07 --- u-boot-env ethaddr +1 WAN *:6E:81 u-boot-env wanaddr **Serial Access:** RX on the board for UART is shorted to ground by resistor R176 therefore it must be removed to use the console but it is not necessary to remove to view boot log optionally, R175 can be replaced with a solder bridge short the resistors R175 and R176 are next to the UART RX pin **Installation:** Method 1: Firmware upgrade page OEM webpage at 192.168.0.1 username and password "admin" Navigate to Settings (gear icon) --> Tools --> Firmware select the factory.bin image confirm and wait 3 minutes Method 2: TFTP recovery Follow TFTP instructions using initramfs.bin use sysupgrade.bin to flash using openwrt web interface **Return to OEM:** MTD partitions should be backed up before flashing using TFTP to boot openwrt without overwriting flash Alternatively, it is possible to edit OEM firmware images to flash MTD partitions in openwrt to restore OEM firmware by removing the OEM header and writing the rest to "firmware" **TFTP recovery:** Requires serial console, reset button does nothing at boot rename initramfs.bin to 'uImageESR900' make available on TFTP server at 192.168.99.8 power board, interrupt boot by pressing '4' rapidly execute tftpboot and bootm **Note on ETH switch registers** Registers must be written to the ethernet switch in order to set up the switch's MAC interface. U-boot can write the registers on it's own which is needed, for example, in a TFTP transfer. The register bits from OEM for the AR8327 switch can be read from interrupted boot (tftpboot, bootm) by adding print lines in the switch driver ar8327.c before 'qca,ar8327-initvals' is parsed from DTS and written. for example: pr_info("0x04 %08x\n", ar8xxx_read(priv, AR8327_REG_PAD0_MODE)); Signed-off-by: Michael Pratt <mcpratt@pm.me>
2023-01-30 18:51:36 +00:00
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca955x_senao_router-dual.dtsi"
/ {
compatible = "engenius,esr900", "qca,qca9558";
model = "EnGenius ESR900";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "amber:power";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
default-state = "on";
};
wlan2g {
label = "blue:wlan2g";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wlan5g {
label = "blue:wlan5g";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wps_amber {
label = "amber:wps";
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
};
wps_blue {
label = "blue:wps";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
};
};
};
&phy0 {
qca,mib-poll-interval = <500>;
qca,ar8327-initvals = <
0x04 0x07680000 /* PORT0 PAD MODE CTRL */
0x10 0x40000000 /* POWER_ON_STRAP */
0x50 0xcf35cf35 /* LED_CTRL0 */
0x54 0xcf35cf35 /* LED_CTRL1 */
0x58 0xcf35cf35 /* LED_CTRL2 */
0x5c 0x03ffff00 /* LED_CTRL3 */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
&usb_phy1 {
status = "okay";
};
&usb1 {
status = "okay";
};
&wmac {
nvmem-cells = <&calibration_art_1000>;
nvmem-cell-names = "calibration";
};
&pcie0 {
status = "okay";
wifi@0,0,0 {
compatible = "pci168c,0033";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&calibration_art_5000>;
nvmem-cell-names = "calibration";
};
};