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38 lines
1.2 KiB
Diff
38 lines
1.2 KiB
Diff
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From be06181f45695ce71536ecb461615ebf6f18011e Mon Sep 17 00:00:00 2001
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From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Date: Tue, 15 Mar 2016 13:40:07 +0530
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Subject: [PATCH 06/93] armv8: fsl-layerscape: Put SMMU config code in
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SMMU_BASE
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It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
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LS1012A are layerscape SoC without SMMU IP.
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So put SMMU configuration code under SMMU_BASE.
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Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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---
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arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
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index 93f4a65..5f5bfb9 100644
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--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
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+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
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@@ -95,11 +95,13 @@ ENTRY(lowlevel_init)
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bl ccn504_set_qos
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#endif
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+#ifdef SMMU_BASE
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/* Set the SMMU page size in the sACR register */
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ldr x1, =SMMU_BASE
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ldr w0, [x1, #0x10]
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orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
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str w0, [x1, #0x10]
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+#endif
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/* Initialize GIC Secure Bank Status */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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--
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1.7.9.5
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