2022-03-27 10:54:03 +00:00
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From patchwork Thu May 28 06:16:48 2020
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From: <chuanjia.liu@mediatek.com>
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To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
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Subject: [PATCH v2 4/4] ARM: dts: mediatek: Update mt7629 PCIe node
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Date: Thu, 28 May 2020 14:16:48 +0800
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Message-ID: <20200528061648.32078-5-chuanjia.liu@mediatek.com>
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Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
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srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
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linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
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linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
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From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
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Remove unused property and add pciecfg node.
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Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
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---
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arch/arm/boot/dts/mt7629-rfb.dts | 3 ++-
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arch/arm/boot/dts/mt7629.dtsi | 23 +++++++++++++----------
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2 files changed, 15 insertions(+), 11 deletions(-)
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--- a/arch/arm/boot/dts/mt7629-rfb.dts
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+++ b/arch/arm/boot/dts/mt7629-rfb.dts
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@@ -149,9 +149,10 @@
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};
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};
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-&pcie {
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+&pcie1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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+ status = "okay";
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};
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&pciephy1 {
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--- a/arch/arm/boot/dts/mt7629.dtsi
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+++ b/arch/arm/boot/dts/mt7629.dtsi
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2022-04-30 14:17:46 +00:00
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@@ -382,16 +382,21 @@
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2022-03-27 10:54:03 +00:00
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#reset-cells = <1>;
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};
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- pcie: pcie@1a140000 {
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+ pciecfg: pciecfg@1a140000 {
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+ compatible = "mediatek,mt7629-pciecfg", "syscon";
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+ reg = <0x1a140000 0x1000>;
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+ };
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+
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+ pcie1: pcie@1a145000 {
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compatible = "mediatek,mt7629-pcie";
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device_type = "pci";
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- reg = <0x1a140000 0x1000>,
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- <0x1a145000 0x1000>;
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- reg-names = "subsys","port1";
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+ reg = <0x1a145000 0x1000>;
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+ reg-names = "port1";
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+ mediatek,pcie-cfg = <&pciecfg>;
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
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- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "pcie_irq";
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clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P1_AUX_EN>,
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2022-04-30 14:17:46 +00:00
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@@ -412,21 +417,19 @@
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2022-03-27 10:54:03 +00:00
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
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+ status = "disabled";
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- pcie1: pcie@1,0 {
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- device_type = "pci";
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+ slot1: pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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- num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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-
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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