mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-24 15:56:49 +00:00
124 lines
1.6 KiB
Plaintext
124 lines
1.6 KiB
Plaintext
|
/dts-v1/;
|
||
|
|
||
|
#include "mt7628an.dtsi"
|
||
|
|
||
|
#include <dt-bindings/gpio/gpio.h>
|
||
|
#include <dt-bindings/input/input.h>
|
||
|
|
||
|
/ {
|
||
|
compatible = "vocore,VoCore2", "mediatek,mt7628an-soc";
|
||
|
model = "VoCore2";
|
||
|
|
||
|
chosen {
|
||
|
bootargs = "console=ttyS2,115200";
|
||
|
};
|
||
|
|
||
|
memory@0 {
|
||
|
device_type = "memory";
|
||
|
reg = <0x0 0x4000000>;
|
||
|
};
|
||
|
|
||
|
gpio-leds {
|
||
|
compatible = "gpio-leds";
|
||
|
|
||
|
status {
|
||
|
label = "vocore2:fuchsia:status";
|
||
|
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
|
||
|
};
|
||
|
};
|
||
|
};
|
||
|
|
||
|
&pinctrl {
|
||
|
state_default: pinctrl0 {
|
||
|
gpio {
|
||
|
ralink,group = "refclk", "gpio";
|
||
|
ralink,function = "gpio";
|
||
|
};
|
||
|
|
||
|
agpio {
|
||
|
ralink,group = "agpio";
|
||
|
ralink,function = "uart2";
|
||
|
};
|
||
|
};
|
||
|
|
||
|
uart1_pins: uart1 {
|
||
|
uart1 {
|
||
|
ralink,group = "uart1";
|
||
|
ralink,function = "uart1";
|
||
|
};
|
||
|
};
|
||
|
|
||
|
uart2_pins: uart2 {
|
||
|
uart2 {
|
||
|
ralink,group = "spis";
|
||
|
ralink,function = "pwm";
|
||
|
};
|
||
|
};
|
||
|
};
|
||
|
|
||
|
&wmac {
|
||
|
status = "okay";
|
||
|
ralink,mtd-eeprom = <&factory 0x4>;
|
||
|
};
|
||
|
|
||
|
&spi0 {
|
||
|
status = "okay";
|
||
|
|
||
|
m25p80@0 {
|
||
|
#address-cells = <1>;
|
||
|
#size-cells = <1>;
|
||
|
compatible = "jedec,spi-nor";
|
||
|
reg = <0>;
|
||
|
spi-max-frequency = <10000000>;
|
||
|
m25p,chunked-io = <32>;
|
||
|
|
||
|
partition@0 {
|
||
|
label = "u-boot";
|
||
|
reg = <0x0 0x30000>;
|
||
|
read-only;
|
||
|
};
|
||
|
|
||
|
partition@30000 {
|
||
|
label = "u-boot-env";
|
||
|
reg = <0x30000 0x10000>;
|
||
|
read-only;
|
||
|
};
|
||
|
|
||
|
factory: partition@40000 {
|
||
|
label = "factory";
|
||
|
reg = <0x40000 0x10000>;
|
||
|
read-only;
|
||
|
};
|
||
|
|
||
|
partition@50000 {
|
||
|
label = "firmware";
|
||
|
reg = <0x50000 0xfb0000>;
|
||
|
};
|
||
|
};
|
||
|
};
|
||
|
|
||
|
&esw {
|
||
|
mediatek,portmap = <0x7>;
|
||
|
mediatek,portdisable = <0x3a>;
|
||
|
};
|
||
|
|
||
|
&i2s {
|
||
|
status = "okay";
|
||
|
};
|
||
|
|
||
|
&gdma {
|
||
|
status = "okay";
|
||
|
};
|
||
|
|
||
|
&pwm {
|
||
|
status = "okay";
|
||
|
};
|
||
|
|
||
|
&uart1 {
|
||
|
status = "okay";
|
||
|
};
|
||
|
|
||
|
&uart2 {
|
||
|
status = "okay";
|
||
|
};
|