2021-03-21 08:45:24 +00:00
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#include "mt7620a_phicomm_k2x.dtsi"
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2018-06-20 16:56:38 +00:00
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/ {
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compatible = "phicomm,k2g", "ralink,mt7620a-soc";
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model = "Phicomm K2G";
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};
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2021-03-21 08:45:24 +00:00
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&partitions {
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partition@50000 {
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reg = <0x50000 0x50000>;
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label = "permanent_config";
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read-only;
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2018-06-20 16:56:38 +00:00
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};
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2021-03-21 08:45:24 +00:00
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partition@a0000 {
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compatible = "denx,uimage";
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reg = <0xa0000 0x760000>;
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label = "firmware";
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2018-06-20 16:56:38 +00:00
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii2_pins &mdio_pins>;
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2020-05-14 13:41:31 +00:00
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2021-04-02 21:50:02 +00:00
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nvmem-cells = <&macaddr_factory_28>;
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nvmem-cell-names = "mac-address";
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2020-05-14 13:41:31 +00:00
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2018-06-20 16:56:38 +00:00
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mediatek,portmap = "llllw";
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port@5 {
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status = "okay";
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phy-handle = <&phy5>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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phy5: ethernet-phy@5 {
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reg = <5>;
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phy-mode = "rgmii";
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};
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};
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};
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&wmac {
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pinctrl-names = "default";
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pinctrl-0 = <&pa_pins>;
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};
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2021-04-02 21:50:02 +00:00
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&factory {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_28: macaddr@28 {
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reg = <0x28 0x6>;
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};
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};
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