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50 lines
1.5 KiB
Diff
50 lines
1.5 KiB
Diff
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From be5f1d59341e48dbe0730253417c52bf79c6c3a7 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Date: Mon, 12 Aug 2013 14:14:49 -0300
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Subject: [PATCH 116/203] mtd: nand: pxa3xx: Allow to set/clear the 'spare
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enable' field
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Some commands (such as the ONFI parameter page read) need to
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clear the 'spare enable' bit. This commit allows to set/clear
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depending on the prepared command, instead of having it always
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set.
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -185,6 +185,7 @@ struct pxa3xx_nand_info {
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int cs;
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int use_ecc; /* use HW ECC ? */
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int use_dma; /* use DMA ? */
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+ int use_spare; /* use spare ? */
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int is_ready;
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unsigned int page_size; /* page size of attached chip */
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@@ -325,6 +326,11 @@ static void pxa3xx_nand_start(struct pxa
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else
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ndcr &= ~NDCR_DMA_EN;
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+ if (info->use_spare)
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+ ndcr |= NDCR_SPARE_EN;
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+ else
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+ ndcr &= ~NDCR_SPARE_EN;
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+
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ndcr |= NDCR_ND_RUN;
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/* clear status bits and run */
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@@ -526,6 +532,7 @@ static int prepare_command_pool(struct p
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info->buf_count = 0;
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info->oob_size = 0;
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info->use_ecc = 0;
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+ info->use_spare = 1;
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info->use_dma = (use_dma) ? 1 : 0;
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info->is_ready = 0;
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info->retcode = ERR_NONE;
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