openwrt/target/linux/bcm27xx/patches-6.6/950-1070-drm-panel-simple-Increase-pixel-clock-on-Pi-7inch-pa.patch

From d5377dd13e91af81f8f31e93532c62216842038c Mon Sep 17 00:00:00 2001
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
Date: Fri, 26 Apr 2024 19:20:41 +0100
Subject: [PATCH 1070/1085] drm/panel-simple: Increase pixel clock on Pi 7inch
 panel

The Toshiba bridge is very fussy and doesn't like the CM3
output when being told to produce a 27.777MHz pixel clock, which
is an almost perfect match to the DSI link integer divider.

Increasing to 30MHz will switch the DSI link from 333MHz to 400MHz
and makes the bridge happy with the same video timing as works
on Pi4.
(Pi4 will be using a link frequency of 375MHz due to a 3GHz
parent PLL).

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
---
 drivers/gpu/drm/panel/panel-simple.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -3417,11 +3417,11 @@ static const struct panel_desc rocktech_
 };
 
 static const struct drm_display_mode raspberrypi_7inch_mode = {
-	.clock = 27777,
+	.clock = 30000,
 	.hdisplay = 800,
-	.hsync_start = 800 + 59,
-	.hsync_end = 800 + 59 + 2,
-	.htotal = 800 + 59 + 2 + 45,
+	.hsync_start = 800 + 131,
+	.hsync_end = 800 + 131 + 2,
+	.htotal = 800 + 131 + 2 + 45,
 	.vdisplay = 480,
 	.vsync_start = 480 + 7,
 	.vsync_end = 480 + 7 + 2,