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86 lines
2.1 KiB
YAML
86 lines
2.1 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/realtek,rtl8300-timer.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Realtek Timer Device Tree Bindings
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maintainers:
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- Markus Stockhausen <markus.stockhausen@gmx.de>
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description: |
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The Realtek SOCs of the RTL83XX and RTL93XX series have at least 5 known
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timers with corresponding interrupt lines . Their speed is derived from the
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Lexra Bus (LXB) by dividers. Each timer has a block of 4 control registers in
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the address range 0xb800xxxx with following start offsets.
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RTL83XX: 0x3100, 0x3110, 0x3120, 0x3130, 0x3140
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RTL93XX: 0x3200, 0x3210, 0x3220, 0x3230, 0x3240
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properties:
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compatible:
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items:
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- enum:
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- realtek,rtl8380-timer
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- realtek,rtl8390-timer
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- realtek,rtl9300-timer
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- const: realtek,otto-timer
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reg:
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minItems: 5
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maxItems: 5
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description:
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List of timer register addresses.
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interrupts:
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minItems: 5
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maxItems: 5
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description:
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List of timer interrupts.
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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additionalProperties: false
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examples:
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- |
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timer0: timer@3100 {
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compatible = "realtek,rtl8380-timer", "realtek,otto-timer";
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reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
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<0x3130 0x10>, <0x3140 0x10>;
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interrupt-parent = <&intc>;
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interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
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clocks = <&ccu CLK_LXB>;
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};
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- |
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timer0: timer@3100 {
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compatible = "realtek,rtl8390-timer", "realtek,otto-timer";
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reg = <0x3100 0x10>, <0x3110 0x10>, <0x3120 0x10>,
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<0x3130 0x10>, <0x3140 0x10>;
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interrupt-parent = <&intc>;
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interrupts = <29 4>, <28 4>, <17 4>, <16 4>, <15 4>;
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clocks = <&ccu CLK_LXB>;
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};
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- |
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timer0: timer@3200 {
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compatible = "realtek,rtl9300-timer", "realtek,otto-timer";
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reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
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<0x3230 0x10>, <0x3240 0x10>;
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interrupt-parent = <&intc>;
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interrupts = <7 4>, <8 4>, <9 4>, <10 4>, <11 4>;
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clocks = <&ccu CLK_LXB>;
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};
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...
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