2020-09-25 20:20:56 +00:00
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|
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/dts-v1/;
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2014-11-06 09:31:31 +00:00
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|
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/ {
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|
#address-cells = <1>;
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|
|
#size-cells = <1>;
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2018-08-22 04:57:48 +00:00
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|
|
compatible = "mediatek,mt7628an-soc";
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2014-11-06 09:31:31 +00:00
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2021-02-22 17:44:31 +00:00
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|
|
aliases {
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|
|
serial0 = &uartlite;
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|
};
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|
2014-11-06 09:31:31 +00:00
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|
cpus {
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2018-07-21 14:17:39 +00:00
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|
|
#address-cells = <1>;
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|
|
#size-cells = <0>;
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|
2014-11-06 09:31:31 +00:00
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|
|
cpu@0 {
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|
|
compatible = "mips,mips24KEc";
|
2018-07-21 14:17:39 +00:00
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|
|
reg = <0>;
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2014-11-06 09:31:31 +00:00
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|
};
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|
|
};
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|
2015-02-19 14:04:41 +00:00
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|
|
chosen {
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|
|
bootargs = "console=ttyS0,57600";
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};
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2018-07-21 14:53:10 +00:00
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cpuintc: cpuintc {
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2014-11-06 09:31:31 +00:00
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|
|
#address-cells = <0>;
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#interrupt-cells = <1>;
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|
|
interrupt-controller;
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|
|
compatible = "mti,cpu-interrupt-controller";
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|
|
};
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|
2024-07-09 16:16:36 +00:00
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|
|
mmc_reg_1v8: regulator-1v8 {
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|
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-always-on;
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|
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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|
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regulator-name = "mmc_io";
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};
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mmc_reg_3v3: regulator-3v3 {
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|
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compatible = "regulator-fixed";
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|
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enable-active-high;
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regulator-always-on;
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|
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "mmc_power";
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};
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2016-05-10 10:41:46 +00:00
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palmbus: palmbus@10000000 {
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2014-11-06 09:31:31 +00:00
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|
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compatible = "palmbus";
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reg = <0x10000000 0x200000>;
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2015-08-17 05:57:18 +00:00
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ranges = <0x0 0x10000000 0x1FFFFF>;
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2014-11-06 09:31:31 +00:00
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#address-cells = <1>;
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#size-cells = <1>;
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2023-06-17 11:30:59 +00:00
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sysc: syscon@0 {
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2023-12-30 11:52:18 +00:00
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|
|
compatible = "ralink,mt7628-sysc", "ralink,mt7688-sysc", "syscon";
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2014-11-06 09:31:31 +00:00
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|
|
reg = <0x0 0x100>;
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2023-06-17 11:30:59 +00:00
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|
|
#clock-cells = <1>;
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|
|
#reset-cells = <1>;
|
2014-11-06 09:31:31 +00:00
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|
|
};
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|
2018-06-08 09:15:17 +00:00
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|
watchdog: watchdog@100 {
|
2023-06-22 13:22:32 +00:00
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|
|
compatible = "mediatek,mt7621-wdt";
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|
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reg = <0x100 0x100>;
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|
|
mediatek,sysctl = <&sysc>;
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2014-11-06 09:31:31 +00:00
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|
|
};
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intc: intc@200 {
|
2024-06-28 07:50:57 +00:00
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|
|
compatible = "ralink,rt2880-intc";
|
2014-11-06 09:31:31 +00:00
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|
|
reg = <0x200 0x100>;
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interrupt-controller;
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|
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#interrupt-cells = <1>;
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|
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|
|
interrupt-parent = <&cpuintc>;
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|
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interrupts = <2>;
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|
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ralink,intc-registers = <0x9c 0xa0
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0x6c 0xa4
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0x80 0x78>;
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|
|
};
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|
2016-05-10 10:41:46 +00:00
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|
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memc: memc@300 {
|
2014-11-06 09:31:31 +00:00
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|
|
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
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reg = <0x300 0x100>;
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|
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interrupt-parent = <&intc>;
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|
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interrupts = <3>;
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|
};
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|
2020-04-09 09:10:03 +00:00
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|
|
gpio: gpio@600 {
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|
|
compatible = "mediatek,mt7621-gpio";
|
2014-11-06 09:31:31 +00:00
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|
|
reg = <0x600 0x100>;
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|
2015-10-01 19:12:14 +00:00
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|
|
interrupt-parent = <&intc>;
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|
|
interrupts = <6>;
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|
2020-04-09 09:10:03 +00:00
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|
|
#interrupt-cells = <2>;
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|
|
interrupt-controller;
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|
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gpio-controller;
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|
|
#gpio-cells = <2>;
|
2014-11-06 09:31:31 +00:00
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|
|
};
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|
2016-05-10 10:41:46 +00:00
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|
|
i2c: i2c@900 {
|
2016-01-07 14:27:45 +00:00
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|
|
compatible = "mediatek,mt7621-i2c";
|
2015-10-19 10:07:54 +00:00
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|
|
reg = <0x900 0x100>;
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|
2024-11-22 10:12:12 +00:00
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|
|
clocks = <&sysc 9>;
|
2023-06-17 11:30:59 +00:00
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|
|
clock-names = "i2c";
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|
|
resets = <&sysc 16>;
|
2015-10-19 10:07:54 +00:00
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|
|
reset-names = "i2c";
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|
|
#address-cells = <1>;
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|
|
|
#size-cells = <0>;
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|
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|
|
status = "disabled";
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|
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|
|
pinctrl-names = "default";
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|
|
pinctrl-0 = <&i2c_pins>;
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|
|
|
};
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|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
i2s: i2s@a00 {
|
2016-02-22 12:49:25 +00:00
|
|
|
compatible = "mediatek,mt7628-i2s";
|
2015-10-19 10:07:54 +00:00
|
|
|
reg = <0xa00 0x100>;
|
|
|
|
|
2024-11-22 10:12:12 +00:00
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|
|
clocks = <&sysc 10>;
|
2023-06-17 11:30:59 +00:00
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|
|
|
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|
|
resets = <&sysc 17>;
|
2015-10-19 10:07:54 +00:00
|
|
|
reset-names = "i2s";
|
|
|
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <10>;
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|
|
|
|
2016-02-22 12:49:25 +00:00
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|
|
txdma-req = <2>;
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|
|
|
rxdma-req = <3>;
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|
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|
|
dmas = <&gdma 4>,
|
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|
|
<&gdma 6>;
|
2015-10-19 10:07:54 +00:00
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|
|
dma-names = "tx", "rx";
|
|
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|
|
status = "disabled";
|
|
|
|
};
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|
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|
2016-05-10 10:41:46 +00:00
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|
|
spi0: spi@b00 {
|
2014-11-06 09:31:31 +00:00
|
|
|
compatible = "ralink,mt7621-spi";
|
|
|
|
reg = <0xb00 0x100>;
|
|
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|
2024-11-22 10:12:12 +00:00
|
|
|
clocks = <&sysc 11>;
|
2023-06-17 11:30:59 +00:00
|
|
|
clock-names = "spi";
|
|
|
|
|
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|
|
resets = <&sysc 18>;
|
2014-11-06 09:31:31 +00:00
|
|
|
reset-names = "spi";
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
2015-10-05 10:26:54 +00:00
|
|
|
#size-cells = <0>;
|
2014-11-06 09:31:31 +00:00
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&spi_pins>;
|
|
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|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2023-06-17 11:30:59 +00:00
|
|
|
uartlite: uart0@c00 {
|
2014-11-06 09:31:31 +00:00
|
|
|
compatible = "ns16550a";
|
|
|
|
reg = <0xc00 0x100>;
|
|
|
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
reg-io-width = <4>;
|
|
|
|
no-loopback-test;
|
|
|
|
|
2024-11-22 10:12:12 +00:00
|
|
|
clocks = <&sysc 13>;
|
2016-05-10 13:23:54 +00:00
|
|
|
|
2023-06-17 11:30:59 +00:00
|
|
|
resets = <&sysc 12>;
|
2014-11-06 09:31:31 +00:00
|
|
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <20>;
|
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&uart0_pins>;
|
|
|
|
};
|
2015-07-24 09:12:21 +00:00
|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
uart1: uart1@d00 {
|
2015-07-24 09:12:21 +00:00
|
|
|
compatible = "ns16550a";
|
|
|
|
reg = <0xd00 0x100>;
|
|
|
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
reg-io-width = <4>;
|
|
|
|
no-loopback-test;
|
|
|
|
|
2024-11-22 10:12:12 +00:00
|
|
|
clocks = <&sysc 14>;
|
2016-05-10 13:23:54 +00:00
|
|
|
|
2023-06-17 11:30:59 +00:00
|
|
|
resets = <&sysc 19>;
|
2015-07-24 09:12:21 +00:00
|
|
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <21>;
|
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&uart1_pins>;
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2016-05-09 04:20:02 +00:00
|
|
|
uart2: uart2@e00 {
|
2015-07-24 09:12:21 +00:00
|
|
|
compatible = "ns16550a";
|
|
|
|
reg = <0xe00 0x100>;
|
|
|
|
|
|
|
|
reg-shift = <2>;
|
|
|
|
reg-io-width = <4>;
|
|
|
|
no-loopback-test;
|
|
|
|
|
2024-11-22 10:12:12 +00:00
|
|
|
clocks = <&sysc 15>;
|
2016-05-10 13:23:54 +00:00
|
|
|
|
2023-06-17 11:30:59 +00:00
|
|
|
resets = <&sysc 20>;
|
2015-07-24 09:12:21 +00:00
|
|
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <22>;
|
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&uart2_pins>;
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
2015-10-19 10:07:54 +00:00
|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
pwm: pwm@5000 {
|
2015-10-19 10:07:54 +00:00
|
|
|
compatible = "mediatek,mt7628-pwm";
|
|
|
|
reg = <0x5000 0x1000>;
|
2019-03-15 10:05:53 +00:00
|
|
|
#pwm-cells = <2>;
|
2015-10-19 10:07:54 +00:00
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
pcm: pcm@2000 {
|
2015-10-19 10:07:54 +00:00
|
|
|
compatible = "ralink,mt7620a-pcm";
|
|
|
|
reg = <0x2000 0x800>;
|
|
|
|
|
2023-06-17 11:30:59 +00:00
|
|
|
resets = <&sysc 11>;
|
2015-10-19 10:07:54 +00:00
|
|
|
reset-names = "pcm";
|
|
|
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <4>;
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
gdma: gdma@2800 {
|
2015-12-02 13:41:22 +00:00
|
|
|
compatible = "ralink,rt3883-gdma";
|
2015-10-19 10:07:54 +00:00
|
|
|
reg = <0x2800 0x800>;
|
|
|
|
|
2023-06-17 11:30:59 +00:00
|
|
|
resets = <&sysc 14>;
|
2015-10-19 10:07:54 +00:00
|
|
|
reset-names = "dma";
|
|
|
|
|
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <7>;
|
|
|
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
#dma-channels = <16>;
|
|
|
|
#dma-requests = <16>;
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
pinctrl: pinctrl {
|
2014-11-06 09:31:31 +00:00
|
|
|
compatible = "ralink,rt2880-pinmux";
|
|
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl-0 = <&state_default>;
|
2015-08-17 05:57:18 +00:00
|
|
|
|
2014-11-06 09:31:31 +00:00
|
|
|
state_default: pinctrl0 {
|
|
|
|
};
|
2015-08-17 05:57:18 +00:00
|
|
|
|
2018-12-06 09:02:29 +00:00
|
|
|
spi_pins: spi_pins {
|
|
|
|
spi_pins {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "spi";
|
|
|
|
function = "spi";
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
};
|
2015-08-17 05:57:18 +00:00
|
|
|
|
2015-10-19 10:07:54 +00:00
|
|
|
spi_cs1_pins: spi_cs1 {
|
|
|
|
spi_cs1 {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "spi cs1";
|
|
|
|
function = "spi cs1";
|
2015-10-19 10:07:54 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2018-12-06 09:02:29 +00:00
|
|
|
i2c_pins: i2c_pins {
|
|
|
|
i2c_pins {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "i2c";
|
|
|
|
function = "i2c";
|
2015-10-19 10:07:54 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2017-11-18 09:51:07 +00:00
|
|
|
i2s_pins: i2s {
|
|
|
|
i2s {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "i2s";
|
|
|
|
function = "i2s";
|
2017-11-18 09:51:07 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2014-11-06 09:31:31 +00:00
|
|
|
uart0_pins: uartlite {
|
2015-07-24 09:12:21 +00:00
|
|
|
uartlite {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "uart0";
|
|
|
|
function = "uart0";
|
2015-07-24 09:12:21 +00:00
|
|
|
};
|
|
|
|
};
|
2015-08-17 05:57:18 +00:00
|
|
|
|
2015-07-24 09:12:21 +00:00
|
|
|
uart1_pins: uart1 {
|
|
|
|
uart1 {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "uart1";
|
|
|
|
function = "uart1";
|
2015-07-24 09:12:21 +00:00
|
|
|
};
|
|
|
|
};
|
2015-08-17 05:57:18 +00:00
|
|
|
|
2015-07-24 09:12:21 +00:00
|
|
|
uart2_pins: uart2 {
|
|
|
|
uart2 {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "uart2";
|
|
|
|
function = "uart2";
|
2015-07-24 09:12:21 +00:00
|
|
|
};
|
|
|
|
};
|
2015-08-17 05:57:18 +00:00
|
|
|
|
2015-07-24 09:12:21 +00:00
|
|
|
sdxc_pins: sdxc {
|
|
|
|
sdxc {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "sdmode";
|
|
|
|
function = "sdxc";
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
};
|
2015-10-19 10:07:54 +00:00
|
|
|
|
|
|
|
pwm0_pins: pwm0 {
|
|
|
|
pwm0 {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "pwm0";
|
|
|
|
function = "pwm0";
|
2015-10-19 10:07:54 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
pwm1_pins: pwm1 {
|
|
|
|
pwm1 {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "pwm1";
|
|
|
|
function = "pwm1";
|
2015-10-19 10:07:54 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2017-11-18 09:51:07 +00:00
|
|
|
pcm_i2s_pins: pcm_i2s {
|
|
|
|
pcm_i2s {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "i2s";
|
|
|
|
function = "pcm";
|
2015-10-19 10:07:54 +00:00
|
|
|
};
|
|
|
|
};
|
2017-11-18 09:51:07 +00:00
|
|
|
|
|
|
|
refclk_pins: refclk {
|
|
|
|
refclk {
|
2020-04-12 12:58:29 +00:00
|
|
|
groups = "refclk";
|
|
|
|
function = "refclk";
|
2017-11-18 09:51:07 +00:00
|
|
|
};
|
|
|
|
};
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
|
2016-02-19 16:38:04 +00:00
|
|
|
usbphy: usbphy@10120000 {
|
2018-04-13 11:13:20 +00:00
|
|
|
compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
|
2016-07-06 19:42:54 +00:00
|
|
|
reg = <0x10120000 0x1000>;
|
2018-04-07 12:02:25 +00:00
|
|
|
#phy-cells = <0>;
|
2014-11-06 09:31:31 +00:00
|
|
|
|
2018-04-07 12:02:25 +00:00
|
|
|
ralink,sysctl = <&sysc>;
|
2023-06-17 11:30:59 +00:00
|
|
|
/* usb phy reset is only controled by RSTCTRL bit 22 */
|
|
|
|
resets = <&sysc 22>, <&sysc 25>;
|
2016-01-04 14:21:17 +00:00
|
|
|
reset-names = "host", "device";
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
|
2024-07-09 16:16:36 +00:00
|
|
|
sdhci: mmc@10130000 {
|
|
|
|
compatible = "mediatek,mt7620-mmc", "ralink,mt7620-sdhci";
|
2016-05-09 06:23:12 +00:00
|
|
|
reg = <0x10130000 0x4000>;
|
2014-11-15 14:35:32 +00:00
|
|
|
|
2024-07-09 16:16:36 +00:00
|
|
|
bus-width = <4>;
|
|
|
|
|
|
|
|
cap-mmc-highspeed;
|
|
|
|
cap-sd-highspeed;
|
|
|
|
|
2024-11-22 10:12:12 +00:00
|
|
|
clocks = <&sysc 16>, <&sysc 16>;
|
2024-07-09 16:16:36 +00:00
|
|
|
clock-names = "source", "hclk";
|
|
|
|
|
|
|
|
disable-wp;
|
|
|
|
|
2014-11-15 14:35:32 +00:00
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <14>;
|
|
|
|
|
2024-07-09 16:16:36 +00:00
|
|
|
max-frequency = <48000000>;
|
|
|
|
|
|
|
|
pinctrl-names = "default", "state_uhs";
|
2015-07-24 09:12:21 +00:00
|
|
|
pinctrl-0 = <&sdxc_pins>;
|
2024-07-09 16:16:36 +00:00
|
|
|
pinctrl-1 = <&sdxc_pins>;
|
|
|
|
|
|
|
|
resets = <&sysc 30>;
|
|
|
|
reset-names = "hrst";
|
|
|
|
|
|
|
|
vmmc-supply = <&mmc_reg_3v3>;
|
|
|
|
vqmmc-supply = <&mmc_reg_1v8>;
|
2015-07-24 09:12:21 +00:00
|
|
|
|
2014-11-15 14:35:32 +00:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
ehci: ehci@101c0000 {
|
2018-08-13 15:14:08 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2016-01-04 14:21:11 +00:00
|
|
|
compatible = "generic-ehci";
|
2014-11-06 09:31:31 +00:00
|
|
|
reg = <0x101c0000 0x1000>;
|
|
|
|
|
2018-04-07 12:02:25 +00:00
|
|
|
phys = <&usbphy>;
|
2015-02-09 12:13:55 +00:00
|
|
|
phy-names = "usb";
|
|
|
|
|
2014-11-06 09:31:31 +00:00
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <18>;
|
2018-08-13 15:14:08 +00:00
|
|
|
|
|
|
|
ehci_port1: port@1 {
|
|
|
|
reg = <1>;
|
|
|
|
#trigger-source-cells = <0>;
|
|
|
|
};
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
ohci: ohci@101c1000 {
|
2018-08-13 15:14:08 +00:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2016-01-04 14:21:11 +00:00
|
|
|
compatible = "generic-ohci";
|
2014-11-06 09:31:31 +00:00
|
|
|
reg = <0x101c1000 0x1000>;
|
|
|
|
|
2018-04-07 12:02:25 +00:00
|
|
|
phys = <&usbphy>;
|
2015-02-09 12:13:55 +00:00
|
|
|
phy-names = "usb";
|
|
|
|
|
2014-11-06 09:31:31 +00:00
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <18>;
|
2018-08-13 15:14:08 +00:00
|
|
|
|
|
|
|
ohci_port1: port@1 {
|
|
|
|
reg = <1>;
|
|
|
|
#trigger-source-cells = <0>;
|
|
|
|
};
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
ethernet: ethernet@10100000 {
|
2014-11-06 09:31:31 +00:00
|
|
|
compatible = "ralink,rt5350-eth";
|
2016-05-09 06:23:12 +00:00
|
|
|
reg = <0x10100000 0x10000>;
|
2014-11-06 09:31:31 +00:00
|
|
|
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
|
|
interrupts = <5>;
|
2015-01-18 20:16:44 +00:00
|
|
|
|
2023-12-10 15:40:39 +00:00
|
|
|
resets = <&sysc 21>, <&sysc 23>;
|
|
|
|
reset-names = "fe", "esw";
|
2015-12-17 09:25:57 +00:00
|
|
|
|
|
|
|
mediatek,switch = <&esw>;
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
|
2015-12-17 09:25:57 +00:00
|
|
|
esw: esw@10110000 {
|
2024-06-28 07:50:57 +00:00
|
|
|
compatible = "ralink,rt3050-esw";
|
2016-05-09 06:23:12 +00:00
|
|
|
reg = <0x10110000 0x8000>;
|
2014-11-06 09:31:31 +00:00
|
|
|
|
2023-12-10 15:40:39 +00:00
|
|
|
resets = <&sysc 24>;
|
|
|
|
reset-names = "ephy";
|
2015-01-18 20:16:44 +00:00
|
|
|
|
2014-11-06 09:31:31 +00:00
|
|
|
interrupt-parent = <&intc>;
|
|
|
|
interrupts = <17>;
|
|
|
|
};
|
|
|
|
|
2016-05-10 10:41:46 +00:00
|
|
|
pcie: pcie@10140000 {
|
2014-11-06 09:31:31 +00:00
|
|
|
compatible = "mediatek,mt7620-pci";
|
|
|
|
reg = <0x10140000 0x100
|
|
|
|
0x10142000 0x100>;
|
|
|
|
|
2014-11-08 14:15:44 +00:00
|
|
|
#address-cells = <3>;
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
2014-11-06 09:31:31 +00:00
|
|
|
interrupt-parent = <&cpuintc>;
|
|
|
|
interrupts = <4>;
|
|
|
|
|
2023-06-17 11:30:59 +00:00
|
|
|
resets = <&sysc 26>;
|
|
|
|
reset-names = "pcie0";
|
2016-05-10 13:23:54 +00:00
|
|
|
|
2014-11-06 09:31:31 +00:00
|
|
|
status = "disabled";
|
|
|
|
|
2014-11-14 16:53:07 +00:00
|
|
|
device_type = "pci";
|
|
|
|
|
|
|
|
bus-range = <0 255>;
|
|
|
|
ranges = <
|
|
|
|
0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
|
|
|
|
0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
|
|
|
|
>;
|
|
|
|
|
2018-07-21 14:19:46 +00:00
|
|
|
pcie0: pcie@0,0 {
|
2014-11-06 09:31:31 +00:00
|
|
|
reg = <0x0000 0 0 0 0>;
|
2014-11-08 14:15:44 +00:00
|
|
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
2014-11-06 09:31:31 +00:00
|
|
|
device_type = "pci";
|
2018-07-21 14:19:46 +00:00
|
|
|
|
|
|
|
ranges;
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|
|
|
|
};
|
2016-02-28 13:21:54 +00:00
|
|
|
|
|
|
|
wmac: wmac@10300000 {
|
|
|
|
compatible = "mediatek,mt7628-wmac";
|
2016-05-09 06:23:12 +00:00
|
|
|
reg = <0x10300000 0x100000>;
|
2016-02-28 13:21:54 +00:00
|
|
|
|
2024-11-22 10:12:12 +00:00
|
|
|
clocks = <&sysc 17>;
|
2023-06-17 11:30:59 +00:00
|
|
|
|
2016-02-28 13:21:54 +00:00
|
|
|
interrupt-parent = <&cpuintc>;
|
|
|
|
interrupts = <6>;
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
};
|
2014-11-06 09:31:31 +00:00
|
|
|
};
|