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60 lines
1.5 KiB
Diff
60 lines
1.5 KiB
Diff
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From cb3ef99c1553565e1dc0301ccd5c1c0fa2d15c15 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 31 Dec 2021 17:56:14 +0100
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Subject: [PATCH] arm64: dts: ipq8074: add CPU clock
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Now that CPU clock is exposed and can be controlled, add the necessary
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properties to the CPU nodes.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -5,6 +5,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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+#include <dt-bindings/clock/qcom,apss-ipq.h>
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/ {
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#address-cells = <2>;
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@@ -38,6 +39,8 @@
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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enable-method = "psci";
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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};
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CPU1: cpu@1 {
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@@ -46,6 +49,8 @@
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enable-method = "psci";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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};
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CPU2: cpu@2 {
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@@ -54,6 +59,8 @@
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enable-method = "psci";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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};
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CPU3: cpu@3 {
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@@ -62,6 +69,8 @@
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enable-method = "psci";
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reg = <0x3>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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};
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L2_0: l2-cache {
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