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52 lines
2.0 KiB
Diff
52 lines
2.0 KiB
Diff
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From d568739f1c21e1768a887ff85611769f782eb64f Mon Sep 17 00:00:00 2001
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From: Baruch Siach <baruch.siach@siklu.com>
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Date: Tue, 21 Jun 2022 11:54:53 +0300
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Subject: [PATCH] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
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The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
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PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
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describe its meaning.
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Link: https://lore.kernel.org/r/3025d5e1d8da64798db6958f9780c4763fbcac47.1655799816.git.baruch@tkos.co.il
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Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++++++++--
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1 file changed, 15 insertions(+), 2 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -69,7 +69,20 @@
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#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
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#define CFG_BRIDGE_SB_INIT BIT(0)
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-#define PCIE_CAP_LINK1_VAL 0x2FD7F
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+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \
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+ 250)
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+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \
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+ 1)
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+#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
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+ PCI_EXP_SLTCAP_PCP | \
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+ PCI_EXP_SLTCAP_MRLSP | \
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+ PCI_EXP_SLTCAP_AIP | \
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+ PCI_EXP_SLTCAP_PIP | \
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+ PCI_EXP_SLTCAP_HPS | \
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+ PCI_EXP_SLTCAP_HPC | \
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+ PCI_EXP_SLTCAP_EIP | \
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+ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
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+ PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
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#define PCIE20_PARF_Q2A_FLUSH 0x1AC
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@@ -1125,7 +1138,7 @@ static int qcom_pcie_post_init_2_3_3(str
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writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
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writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
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- writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
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+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
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val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
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val &= ~PCI_EXP_LNKCAP_ASPMS;
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