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35 lines
1.2 KiB
Diff
35 lines
1.2 KiB
Diff
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From a0d015caa8ddfd37ae8cbfc7aec1d614b5ad3b78 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Mon, 15 Feb 2016 17:31:41 -0800
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Subject: [PATCH 292/304] drm/vc4: Fix setting of vertical timings in the CRTC.
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It looks like when I went to add the interlaced bits, I just took the
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existing PV_VERT* block and indented it, instead of copy and pasting
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it first. Without this, changing resolution never worked.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit a7c5047d1ce178dd2b1fa577fc8909ad663d56d5)
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 10 ++++++++++
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1 file changed, 10 insertions(+)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -217,6 +217,16 @@ static void vc4_crtc_mode_set_nofb(struc
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PV_HORZB_HFP) |
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VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
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+ CRTC_WRITE(PV_VERTA,
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+ VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
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+ PV_VERTA_VBP) |
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+ VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
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+ PV_VERTA_VSYNC));
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+ CRTC_WRITE(PV_VERTB,
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+ VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
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+ PV_VERTB_VFP) |
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+ VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
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+
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if (interlace) {
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CRTC_WRITE(PV_VERTA_EVEN,
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
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