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95 lines
2.7 KiB
Diff
95 lines
2.7 KiB
Diff
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From a9ab8f5de2fc752e37918cfd5dcd16d625d9ecb2 Mon Sep 17 00:00:00 2001
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From: Shawn Guo <shawn.guo@linaro.org>
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Date: Wed, 29 Sep 2021 11:42:51 +0800
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Subject: [PATCH] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes
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IPQ8074 PCIe PHY nodes are broken in the many ways:
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- '#address-cells', '#size-cells' and 'ranges' are missing.
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- Child phy/lane node is missing, and the child properties like
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'#phy-cells' and 'clocks' are mistakenly put into parent node.
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- The clocks properties for parent node are missing.
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Fix them to get the nodes comply with the bindings schema.
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20210929034253.24570-9-shawn.guo@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 +++++++++++++++++++++------
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1 file changed, 36 insertions(+), 10 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -174,34 +174,60 @@
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status = "disabled";
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};
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- pcie_phy0: phy@86000 {
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+ pcie_qmp0: phy@86000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x00086000 0x1000>;
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- #phy-cells = <0>;
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- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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- clock-names = "pipe_clk";
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- clock-output-names = "pcie20_phy0_pipe_clk";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
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+ <&gcc GCC_PCIE0_AHB_CLK>;
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+ clock-names = "aux", "cfg_ahb";
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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+
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+ pcie_phy0: phy@86200 {
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+ reg = <0x86200 0x16c>,
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+ <0x86400 0x200>,
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+ <0x86800 0x4f4>;
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+ #phy-cells = <0>;
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+ #clock-cells = <0>;
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+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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+ clock-names = "pipe0";
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+ clock-output-names = "pcie_0_pipe_clk";
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+ };
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};
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- pcie_phy1: phy@8e000 {
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+ pcie_qmp1: phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x0008e000 0x1000>;
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- #phy-cells = <0>;
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- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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- clock-names = "pipe_clk";
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- clock-output-names = "pcie20_phy1_pipe_clk";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ clocks = <&gcc GCC_PCIE1_AUX_CLK>,
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+ <&gcc GCC_PCIE1_AHB_CLK>;
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+ clock-names = "aux", "cfg_ahb";
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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<&gcc GCC_PCIE1PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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+
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+ pcie_phy1: phy@8e200 {
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+ reg = <0x8e200 0x16c>,
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+ <0x8e400 0x200>,
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+ <0x8e800 0x4f4>;
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+ #phy-cells = <0>;
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+ #clock-cells = <0>;
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+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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+ clock-names = "pipe0";
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+ clock-output-names = "pcie_1_pipe_clk";
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+ };
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};
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prng: rng@e3000 {
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