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46 lines
1.9 KiB
Diff
46 lines
1.9 KiB
Diff
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Subject: [PATCH] clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
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Date: Tue, 6 Aug 2024 16:29:02 +0200
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Message-Id: <20240806142902.224164-1-sergio.paracuellos@gmail.com>
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Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
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set some peripherals that has this clock as their parent. When this driver
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was mainlined we could not find any active users of this SoC so we cannot
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perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
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device which uses this SoC appear and reported some issues in openWRT:
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- https://github.com/openwrt/openwrt/issues/16054
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The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
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has a not defined 'periph' clock as parent. Hence, introduce it to have a
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properly working clock plan for this SoC.
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Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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---
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drivers/clk/ralink/clk-mtmips.c | 9 +++++++--
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1 file changed, 7 insertions(+), 2 deletions(-)
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--- a/drivers/clk/ralink/clk-mtmips.c
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+++ b/drivers/clk/ralink/clk-mtmips.c
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@@ -267,6 +267,11 @@ static struct mtmips_clk_fixed rt305x_fi
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CLK_FIXED("xtal", NULL, 40000000)
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};
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+static struct mtmips_clk_fixed rt3383_fixed_clocks[] = {
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+ CLK_FIXED("xtal", NULL, 40000000),
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+ CLK_FIXED("periph", "xtal", 40000000)
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+};
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+
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static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
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CLK_FIXED("periph", "xtal", 40000000)
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};
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@@ -779,8 +784,8 @@ static const struct mtmips_clk_data rt33
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static const struct mtmips_clk_data rt3883_clk_data = {
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.clk_base = rt3883_clks_base,
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.num_clk_base = ARRAY_SIZE(rt3883_clks_base),
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- .clk_fixed = rt305x_fixed_clocks,
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- .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
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+ .clk_fixed = rt3383_fixed_clocks,
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+ .num_clk_fixed = ARRAY_SIZE(rt3383_fixed_clocks),
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.clk_factor = NULL,
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.num_clk_factor = 0,
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.clk_periph = rt5350_pherip_clks,
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