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95 lines
2.2 KiB
Plaintext
95 lines
2.2 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/leds/common.h>
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#include "mt7628an_xiaomi_mi-router-4.dtsi"
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/ {
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compatible = "xiaomi,mi-router-4a-100m-intl-v2", "mediatek,mt7628an-soc";
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model = "Xiaomi Mi Router 4A (100M International Edition V2)";
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aliases {
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led-boot = &led_power_yellow;
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led-failsafe = &led_power_yellow;
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led-running = &led_power_blue;
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led-upgrade = &led_power_yellow;
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label-mac-device = ðernet;
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};
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leds {
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compatible = "gpio-leds";
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led_power_blue: power_blue {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
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};
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led_power_yellow: power_yellow {
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
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};
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wan {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_WAN;
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gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&partitions {
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partition@60000 {
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label = "overlay";
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reg = <0x60000 0x100000>;
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read-only;
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};
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partition@160000 {
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label = "firmware";
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reg = <0x160000 0xea0000>;
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compatible = "denx,uimage";
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};
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};
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&pcie {
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status = "okay";
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};
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&eeprom_factory_8000 {
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/* MT7613 has different eeprom size '0x4da8' */
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/* See https://github.com/openwrt/openwrt/pull/13587 */
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/* You can also see this in mt76/mt7615/eeprom.h: */
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/* MT7615_EEPROM_FULL_SIZE = MT7615_EEPROM_TXDPD_OFFSET + \ */
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/* MT7615_EEPROM_TXDPD_COUNT * MT7615_EEPROM_TXDPD_SIZE */
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/* where MT7615_EEPROM_TXDPD_OFFSET is 1024 + 256 * 34 = 9728: */
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/* MT7615_EEPROM_SIZE(1024 defined in mt7615.h) + \ */
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/* MT7615_EEPROM_DCOC_COUNT(34) * MT7615_EEPROM_DCOC_SIZE(256)*/
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/* where MT7615_EEPROM_TXDPD_COUNT = 44 + 3 = 47 */
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/* and MT7615_EEPROM_TXDPD_SIZE = 216. */
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/* Altogether it will be 19880 or 0x4da8. */
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reg = <0x8000 0x4da8>;
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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nvmem-cells = <&eeprom_factory_8000>;
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nvmem-cell-names = "eeprom";
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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ðernet {
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nvmem-cells = <&macaddr_factory_4 (-1)>;
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nvmem-cell-names = "mac-address";
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};
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&esw {
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mediatek,portmap = <0x3e>;
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mediatek,portdisable = <0x2a>;
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};
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