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39 lines
1.6 KiB
Diff
39 lines
1.6 KiB
Diff
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From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001
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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Date: Mon, 6 Mar 2023 15:05:21 +0100
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Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set
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critical clock
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Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
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flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.
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Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
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Tested-by: Daniel Golle <daniel@makrotopia.org>
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Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +---
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1 file changed, 1 insertion(+), 3 deletions(-)
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--- a/drivers/clk/mediatek/clk-mt7986-apmixed.c
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+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c
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@@ -42,7 +42,7 @@
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"clkxtal")
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static const struct mtk_pll_data plls[] = {
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- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
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+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
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0x0200, 4, 0, 0x0204, 0),
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PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
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0x0210, 4, 0, 0x0214, 0),
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@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru
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mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
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-
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r) {
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pr_err("%s(): could not register clock provider: %d\n",
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