2020-10-24 22:52:47 +00:00
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From: Nick Hainke <vincent@systemli.org>
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Date: Sun, 25 Oct 2020 00:52:47 +0200
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Subject: [PATCH] ath79: fix block protection clearing
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The block protection bits of macronix do not match the implementation.
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The chip has 3 BP bits. Bit 5 is actually the third BP but here the
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5th bit is SR_TB. Therefore the patch adds SR_TB to the mask. In the
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4.19er kernel the whole register was simply set to 0.
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The wrong implementation did not remove the block protection. This led
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to jffs2 errors in the form of:
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"jffs2: Newly-erased block contained word 0x19852003 at offset 0x..."
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This caused inconsistent memory and other errors.
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Suggested-by: David Bauer <mail@david-bauer.net>
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Signed-off-by: Nick Hainke <vincent@systemli.org>
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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2020-12-21 15:06:01 +00:00
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@@ -1985,7 +1985,7 @@ static int sr2_bit7_quad_enable(struct s
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2020-10-24 22:52:47 +00:00
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static int spi_nor_clear_sr_bp(struct spi_nor *nor)
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{
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int ret;
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- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
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+ u8 mask = SR_TB | SR_BP2 | SR_BP1 | SR_BP0;
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2020-12-21 15:06:01 +00:00
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if (nor->flags & SNOR_F_HAS_4BIT_BP)
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mask |= SR_BP3;
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