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openwrt/target/linux/lantiq/dts/ar9.dtsi

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lantiq: Sanitize device tree files The device tree file of ARV752DPW uses numbers/hex values for gpio states and input event codes. This cleans it up and uses the available macros from header files. This way the functions are easier to read and comprehend. Signed-off-by: Andreas Eberlein <foodeas@aeberlein.de> [sanitize all device tree files] Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-09-29 16:22:55 +00:00
#include <dt-bindings/gpio/gpio.h>
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,xway", "lantiq,ar9";
lantiq: specify console using stdout-path instead of cmdline argument Use devicetree's /chosen/stdout-path instead of the kernel command line (embedded in the .dts-files) to specify the serial console. Using the chosen node is recommended on devicetree based platforms. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
2016-12-11 20:55:00 +00:00
aliases {
serial0 = &asc1;
};
chosen {
stdout-path = "serial0:115200n8";
};
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
cpus {
cpu@0 {
compatible = "mips,mips34K";
};
};
lantiq: add 3.18 support Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44348
2015-02-09 12:13:25 +00:00
memory@0 {
device_type = "memory";
};
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
biu@1F800000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,biu", "simple-bus";
reg = <0x1F800000 0x800000>;
ranges = <0x0 0x1F800000 0x7FFFFF>;
icu0: icu@80200 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "lantiq,icu";
reg = <0x80200 0x28
0x80228 0x28
0x80250 0x28
0x80278 0x28
0x802a0 0x28>;
};
watchdog@803F0 {
compatible = "lantiq,wdt";
reg = <0x803F0 0x10>;
};
};
sram@1F000000 {
#address-cells = <1>;
#size-cells = <1>;
lantiq: Make the ar9.dtsi sram node match "simple-bus" All other SoC types are using "lantiq,sram" and "simple-bus" to ensure that all child nodes are set up correctly during linux kernel initialization (plat_of_setup(void) in arch/mips/lantiq/prom.c). Without this some of sram child nodes might not be parsed. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48548
2016-01-29 00:42:50 +00:00
compatible = "lantiq,sram", "simple-bus";
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
reg = <0x1F000000 0x800000>;
ranges = <0x0 0x1F000000 0x7FFFFF>;
eiu0: eiu@101000 {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "lantiq,eiu-xway";
reg = <0x101000 0x1000>;
interrupt-parent = <&icu0>;
lantiq: use new property name for eiu irqs Signed-off-by: John Crispin <john@phrozen.org>
2016-06-07 16:59:52 +00:00
lantiq,eiu-irqs = <166 135 66 40 41 42>;
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
};
pmu0: pmu@102000 {
compatible = "lantiq,pmu-xway";
reg = <0x102000 0x1000>;
};
cgu0: cgu@103000 {
compatible = "lantiq,cgu-xway";
reg = <0x103000 0x1000>;
#clock-cells = <1>;
};
rcu0: rcu@203000 {
compatible = "lantiq,rcu-xway";
reg = <0x203000 0x1000>;
};
};
fpi@10000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "lantiq,fpi", "simple-bus";
ranges = <0x0 0x10000000 0xEEFFFFF>;
reg = <0x10000000 0xEF00000>;
localbus@0 {
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
1 0 0x4000000 0x4000010>; /* addsel1 */
compatible = "lantiq,localbus", "simple-bus";
};
gptu@E100A00 {
compatible = "lantiq,gptu-xway";
reg = <0xE100A00 0x100>;
interrupt-parent = <&icu0>;
interrupts = <126 127 128 129 130 131>;
};
asc0: serial@E100400 {
compatible = "lantiq,asc";
reg = <0xE100400 0x400>;
interrupt-parent = <&icu0>;
interrupts = <104 105 106>;
status = "disabled";
lantiq: Add the SPI node to ar9.dtsi and vr9.dtsi This allows devices to use SPI without having to re-define (and thus duplicating) the whole SPI node. By default SPI is disabled (as before) because only few devices need it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48286
2016-01-17 19:55:17 +00:00
};
spi: spi@E100800 {
lantiq: Switch to the new SPI driver Compared to the "old" driver: - Each device must assign a pinctrl setting to the SPI node to allow the new SPI driver to configure the SPI pins. While here we are also using separate input and output settings so we are independent of whether the bootloader configures the pins correctly. - We use the new "compatible" strings to make the driver choose the correct number of chip-selects for each SoC. - The new driver starts counting the chip-selects at 1 (instead of 0, like the old one did). Thus we have to adjust the devices accordingly. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48293
2016-01-17 19:56:03 +00:00
compatible = "lantiq,xrx100-spi";
lantiq: Add the SPI node to ar9.dtsi and vr9.dtsi This allows devices to use SPI without having to re-define (and thus duplicating) the whole SPI node. By default SPI is disabled (as before) because only few devices need it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48286
2016-01-17 19:55:17 +00:00
reg = <0xE100800 0x100>;
interrupt-parent = <&icu0>;
interrupts = <22 23 24>;
lantiq: Switch to the new SPI driver Compared to the "old" driver: - Each device must assign a pinctrl setting to the SPI node to allow the new SPI driver to configure the SPI pins. While here we are also using separate input and output settings so we are independent of whether the bootloader configures the pins correctly. - We use the new "compatible" strings to make the driver choose the correct number of chip-selects for each SoC. - The new driver starts counting the chip-selects at 1 (instead of 0, like the old one did). Thus we have to adjust the devices accordingly. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48293
2016-01-17 19:56:03 +00:00
interrupt-names = "spi_rx", "spi_tx", "spi_err",
"spi_frm";
lantiq: Add the SPI node to ar9.dtsi and vr9.dtsi This allows devices to use SPI without having to re-define (and thus duplicating) the whole SPI node. By default SPI is disabled (as before) because only few devices need it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48286
2016-01-17 19:55:17 +00:00
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
};
gpio: pinmux@E100B10 {
lantiq: Use the new pinctrl compatible strings These were introduced in upstream commit be14811c03cf "pinctrl/lantiq: introduce new dedicated devicetree bindings" and finally allow us to use the individual pins within our dts (for example spi_clk, etc.). Please note that this changes the number of GPIOs which are available for some SoCs. VRX200 SoCs for example only have 50 pins, but previously 56 pins were exposed. This means that all places which are using hardcoded GPIO numbers (which are not passed via device-tree) need to be adjusted (because the first GPIO number is now 462, instead of 456). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 48284
2016-01-17 19:55:04 +00:00
compatible = "lantiq,xrx100-pinctrl";
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
#gpio-cells = <2>;
gpio-controller;
reg = <0xE100B10 0xA0>;
};
asc1: serial@E100C00 {
compatible = "lantiq,asc";
reg = <0xE100C00 0x400>;
interrupt-parent = <&icu0>;
interrupts = <112 113 114>;
};
ifxhcd@E101000 {
lantiq: update USB controller initialization This adds USB initialization fixes for Danube, Amazon SE and xrx300 and should fix the clock on at least Danube which hopefully closes FS#351. The xrx200 usb driver now uses more memory for the dwc2 fifos, this was increased in the chip compared to ar9. This is based in part on the vendor documentation and the vendor code base as a reference. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2017-01-06 17:37:40 +00:00
compatible = "lantiq,arx100-usb", "lantiq,ifxhcd-arx100";
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
reg = <0xE101000 0x1000
0xE120000 0x3f000>;
interrupt-parent = <&icu0>;
interrupts = <62 91>;
lantiq: update USB controller initialization This adds USB initialization fixes for Danube, Amazon SE and xrx300 and should fix the clock on at least Danube which hopefully closes FS#351. The xrx200 usb driver now uses more memory for the dwc2 fifos, this was increased in the chip compared to ar9. This is based in part on the vendor documentation and the vendor code base as a reference. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2017-01-06 17:37:40 +00:00
dr_mode = "host";
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
status = "disabled";
};
lantiq: Introduce DWC2 compatible DTS definitions for AR9 USB Since the AR9 USB is very similar to the VR9 USB it too can be used with the upstream DWC2 driver. Here are the DTS definitions which make it compatible with the DWC2 driver. Signed-off-by: Antti Seppälä <a.seppala@gmail.com> SVN-Revision: 46914
2015-09-14 20:08:07 +00:00
ifxhcd@E106000 {
lantiq: update USB controller initialization This adds USB initialization fixes for Danube, Amazon SE and xrx300 and should fix the clock on at least Danube which hopefully closes FS#351. The xrx200 usb driver now uses more memory for the dwc2 fifos, this was increased in the chip compared to ar9. This is based in part on the vendor documentation and the vendor code base as a reference. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2017-01-06 17:37:40 +00:00
compatible = "lantiq,arx100-usb";
lantiq: Introduce DWC2 compatible DTS definitions for AR9 USB Since the AR9 USB is very similar to the VR9 USB it too can be used with the upstream DWC2 driver. Here are the DTS definitions which make it compatible with the DWC2 driver. Signed-off-by: Antti Seppälä <a.seppala@gmail.com> SVN-Revision: 46914
2015-09-14 20:08:07 +00:00
reg = <0xE106000 0x1000
0xE1E0000 0x3f000>;
interrupt-parent = <&icu0>;
interrupts = <91>;
lantiq: update USB controller initialization This adds USB initialization fixes for Danube, Amazon SE and xrx300 and should fix the clock on at least Danube which hopefully closes FS#351. The xrx200 usb driver now uses more memory for the dwc2 fifos, this was increased in the chip compared to ar9. This is based in part on the vendor documentation and the vendor code base as a reference. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2017-01-06 17:37:40 +00:00
dr_mode = "host";
lantiq: Introduce DWC2 compatible DTS definitions for AR9 USB Since the AR9 USB is very similar to the VR9 USB it too can be used with the upstream DWC2 driver. Here are the DTS definitions which make it compatible with the DWC2 driver. Signed-off-by: Antti Seppälä <a.seppala@gmail.com> SVN-Revision: 46914
2015-09-14 20:08:07 +00:00
status = "disabled";
};
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
deu@E103100 {
more devicetree fixes SVN-Revision: 34824
2012-12-21 13:47:55 +00:00
compatible = "lantiq,deu-arx100";
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
reg = <0xE103100 0xf00>;
};
dma0: dma@E104100 {
compatible = "lantiq,dma-xway";
reg = <0xE104100 0x800>;
};
ebu0: ebu@E105300 {
compatible = "lantiq,ebu-xway";
reg = <0xE105300 0x100>;
};
mei@E116000 {
compatible = "lantiq,mei-xway";
interrupt-parent = <&icu0>;
interrupts = <63>;
};
etop@E180000 {
compatible = "lantiq,etop-xway";
reg = <0xE180000 0x40000
0xE108000 0x200>;
interrupt-parent = <&icu0>;
interrupts = <73 72>;
more board file fixes SVN-Revision: 34788
2012-12-19 15:17:11 +00:00
mac-address = [ 00 11 22 33 44 55 ];
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
};
ppe@E234000 {
ar9 did not load atm driver properly SVN-Revision: 34840
2012-12-22 10:16:52 +00:00
compatible = "lantiq,ppe-arx100";
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
interrupt-parent = <&icu0>;
interrupts = <96>;
};
pci0: pci@E105400 {
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
compatible = "lantiq,pci-xway";
bus-range = <0x0 0x0>;
ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
reg = <0x7000000 0x8000 /* config space */
0xE105400 0x400>; /* pci bridge */
lantiq,bus-clock = <33333333>;
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <0x7000 0 0 1 &icu0 30 1>;
req-mask = <0x1>;
};
};
adsl {
more devicetree fixes SVN-Revision: 34824
2012-12-21 13:47:55 +00:00
compatible = "lantiq,adsl-arx100";
add devicetrees SVN-Revision: 34691
2012-12-15 02:00:20 +00:00
};
};
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