openwrt/target/linux/pistachio/patches-6.1/903-MIPS-DTS-img-marduk-Add-NXP-SC16IS752IPW.patch

From ad4eba0c36ce8af6ab9ea1bc163e4c1ac7c271c3 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat, 15 Aug 2020 16:09:02 +0200
Subject: [PATCH 903/904] MIPS: DTS: img: marduk: Add NXP SC16IS752IPW

Add NXP SC16IS752IPW SPI-UART controller to device tree.

This controller drives 2 UARTs and 7 LEDs on the board.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
 arch/mips/boot/dts/img/pistachio_marduk.dts | 51 +++++++++++++++++++++
 1 file changed, 51 insertions(+)

--- a/arch/mips/boot/dts/img/pistachio_marduk.dts
+++ b/arch/mips/boot/dts/img/pistachio_marduk.dts
@@ -46,6 +46,46 @@
 		regulator-max-microvolt = <1800000>;
 	};
 
+	/* EXT clock from ca8210 is fed to sc16is752 */
+	ca8210_ext_clk: ca8210-ext-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <16000000>;
+		clock-output-names = "ca8210_ext_clock";
+	};
+
+	gpioleds {
+		compatible = "gpio-leds";
+		user1 {
+			label = "marduk:red:user1";
+			gpios = <&sc16is752 0 GPIO_ACTIVE_LOW>;
+		};
+		user2 {
+			label = "marduk:red:user2";
+			gpios = <&sc16is752 1 GPIO_ACTIVE_LOW>;
+		};
+		user3 {
+			label = "marduk:red:user3";
+			gpios = <&sc16is752 2 GPIO_ACTIVE_LOW>;
+		};
+		user4 {
+			label = "marduk:red:user4";
+			gpios = <&sc16is752 3 GPIO_ACTIVE_LOW>;
+		};
+		user5 {
+			label = "marduk:red:user5";
+			gpios = <&sc16is752 4 GPIO_ACTIVE_LOW>;
+		};
+		user6 {
+			label = "marduk:red:user6";
+			gpios = <&sc16is752 5 GPIO_ACTIVE_LOW>;
+		};
+		user7 {
+			label = "marduk:red:user7";
+			gpios = <&sc16is752 6 GPIO_ACTIVE_LOW>;
+		};
+	};
+
 	led-controller {
 		compatible = "pwm-leds";
 
@@ -96,6 +136,17 @@
 		extclock-freq = <16000000>;
 		extclock-gpio = <2>;
 	};
+
+	sc16is752: sc16is752@1 {
+		compatible = "nxp,sc16is752";
+		reg = <1>;
+		clocks = <&ca8210_ext_clk>;
+		spi-max-frequency = <4000000>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
 
 &spfi1 {