2018-05-07 10:07:32 +00:00
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From 9ff279fef1a47a152993bf23f8d75fd233c27015 Mon Sep 17 00:00:00 2001
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From: Chaotian Jing <chaotian.jing@mediatek.com>
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Date: Mon, 16 Oct 2017 09:46:28 +0800
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Subject: [PATCH 142/224] mmc: dt-bindings: Add reg/source_cg/latch-ck for
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Mediatek MMC bindings
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Change the comptiable for support of multi-platform
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Make compatible explicit, as MMC host of mt8173 has difference with
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mt8135(mt8173 supports hs400 and hs400_tune),so that need separate
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mt8173/mt8135 compatible name.
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Add description for reg
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Add description for source_cg
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Add description for mediatek,latch-ck
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Note that source_cg and mediatek,latch-ck are optional for some projects,
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eg, MT2701 do not have source_cg, and MT2712 do not need
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mediatek,latch-ck
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Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
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Acked-by: Rob Herring <robh@kernel.org>
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Tested-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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Documentation/devicetree/bindings/mmc/mtk-sd.txt | 18 +++++++++++++++---
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1 file changed, 15 insertions(+), 3 deletions(-)
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--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
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+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
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2018-06-29 20:29:06 +00:00
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@@ -7,10 +7,18 @@ This file documents differences between
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2018-05-07 10:07:32 +00:00
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and the properties used by the msdc driver.
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Required properties:
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-- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"
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+- compatible: value should be either of the following.
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+ "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
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+ "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
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+ "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
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+ "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
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+- reg: physical base address of the controller and length
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- interrupts: Should contain MSDC interrupt number
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-- clocks: MSDC source clock, HCLK
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-- clock-names: "source", "hclk"
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+- clocks: Should contain phandle for the clock feeding the MMC controller
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+- clock-names: Should contain the following:
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+ "source" - source clock (required)
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+ "hclk" - HCLK which used for host (required)
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+ "source_cg" - independent source clock gate (required for MT2712)
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- pinctrl-names: should be "default", "state_uhs"
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- pinctrl-0: should contain default/high speed pin ctrl
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- pinctrl-1: should contain uhs mode pin ctrl
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@@ -30,6 +38,10 @@ Optional properties:
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- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
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If present,HS400 command responses are sampled on rising edges.
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If not present,HS400 command responses are sampled on falling edges.
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+- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
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+ error caused by stop clock(fifo full)
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+ Valid range = [0:0x7]. if not present, default value is 0.
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+ applied to compatible "mediatek,mt2701-mmc".
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Examples:
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mmc0: mmc@11230000 {
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