2020-09-25 20:20:56 +00:00
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#include "mt7628an.dtsi"
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2018-10-22 15:21:16 +00:00
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "wavlink,wl-wn570ha1", "mediatek,mt7628an-soc";
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model = "Wavlink WL-WN570HA1";
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2018-12-30 11:17:25 +00:00
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keys {
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2019-09-20 12:03:02 +00:00
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compatible = "gpio-keys";
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2018-10-22 15:21:16 +00:00
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reset {
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label = "reset";
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2020-04-09 09:10:03 +00:00
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gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
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2018-10-22 15:21:16 +00:00
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linux,code = <KEY_RESTART>;
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};
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};
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2018-12-30 11:42:53 +00:00
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leds {
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2018-10-22 15:21:16 +00:00
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compatible = "gpio-leds";
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power {
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2020-09-27 17:40:51 +00:00
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label = "green:power";
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2020-04-09 09:10:03 +00:00
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gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
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2018-10-22 15:21:16 +00:00
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default-state = "keep";
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};
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wan {
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2020-09-27 17:40:51 +00:00
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label = "green:wan";
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2020-04-09 09:10:03 +00:00
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gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
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2018-10-22 15:21:16 +00:00
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};
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wifi-high {
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2020-09-27 17:40:51 +00:00
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label = "green:wifi-high";
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2020-04-09 09:10:03 +00:00
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gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
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2018-10-22 15:21:16 +00:00
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};
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wifi-med {
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2020-09-27 17:40:51 +00:00
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label = "green:wifi-med";
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2020-04-09 09:10:03 +00:00
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gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
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2018-10-22 15:21:16 +00:00
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};
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wifi-low {
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2020-09-27 17:40:51 +00:00
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label = "green:wifi-low";
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2020-04-09 09:10:03 +00:00
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gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
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2018-10-22 15:21:16 +00:00
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};
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wifi {
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2020-09-27 17:40:51 +00:00
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label = "green:wifi";
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2020-04-09 09:10:03 +00:00
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gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
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2018-10-22 15:21:16 +00:00
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};
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};
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};
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2019-12-22 20:26:01 +00:00
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&state_default {
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gpio {
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2020-04-12 12:58:29 +00:00
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groups = "i2c", "wled_an", "p0led_an", "wdt", "refclk";
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function = "gpio";
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2018-10-22 15:21:16 +00:00
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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reg = <0x0000 0 0 0 0>;
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2023-10-02 02:12:02 +00:00
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nvmem-cells = <&eeprom_factory_8000>;
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nvmem-cell-names = "eeprom";
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2018-10-22 15:21:16 +00:00
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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2023-10-02 02:12:02 +00:00
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compatible = "nvmem-cells";
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2018-10-22 15:21:16 +00:00
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label = "factory";
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reg = <0x40000 0x10000>;
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2023-10-02 02:12:02 +00:00
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#address-cells = <1>;
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#size-cells = <1>;
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2018-10-22 15:21:16 +00:00
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read-only;
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2023-10-02 02:12:02 +00:00
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x400>;
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};
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2023-10-02 02:12:02 +00:00
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eeprom_factory_8000: eeprom@8000 {
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reg = <0x8000 0x200>;
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};
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2023-10-02 02:12:02 +00:00
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macaddr_factory_2e: macaddr@2e {
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reg = <0x2e 0x6>;
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};
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2018-10-22 15:21:16 +00:00
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};
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partition@50000 {
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compatible = "denx,uimage";
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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&wmac {
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status = "okay";
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2021-08-17 12:07:57 +00:00
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2023-10-02 02:12:02 +00:00
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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2018-10-22 15:21:16 +00:00
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};
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ðernet {
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2021-04-02 21:50:02 +00:00
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nvmem-cells = <&macaddr_factory_2e>;
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nvmem-cell-names = "mac-address";
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ramips: mt76x8: fix bogus mediatek,portmap
mt76x8 uses esw_rt3050 driver, which does not accept mediatek,portmap with
string values. Convert the strings to integers to make it work.
According to its switch setup, WRTnode 2P/2R have a WAN port at port 0,
so the correct value should be 0x3e.
tplink_8m.dtsi uses "llllw", but it does not match switch setups of any
device using the DTSI. Remove it from the DTSI and add correct value to DTS
for each device.
These devices have a WAN port at port 0. Set the value to 0x3e.
- tplink,archer-c20-v4
- tplink,archer-c50-v3
- tplink,tl-mr3420-v5
- tplink,tl-wr840n-v4
- tplink,tl-wr841n-v13
- tplink,tl-wr842n-v5
These devices have only one ethernet port. They don't need portmap setting.
- tplink,tl-wa801nd-v5
- tplink,tl-wr802n-v4
- tplink,tl-wr902ac-v3
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
2020-01-01 12:34:10 +00:00
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};
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&esw {
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mediatek,portmap = <0x2f>;
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2018-10-22 15:21:16 +00:00
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};
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